1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2013 Boundary Devices 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Device Configuration Data (DCD) 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Each entry must have the format: 9*4882a593Smuzhiyun * Addr-type Address Value 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * where: 12*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 13*4882a593Smuzhiyun * Address absolute address of the register 14*4882a593Smuzhiyun * value value to be stored in the register 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/* set the default clock gate to save power */ 18*4882a593SmuzhiyunDATA 4, CCM_CCGR0, 0x00c03f3f 19*4882a593SmuzhiyunDATA 4, CCM_CCGR1, 0x0030fcff 20*4882a593SmuzhiyunDATA 4, CCM_CCGR2, 0x0fffcfc0 21*4882a593SmuzhiyunDATA 4, CCM_CCGR3, 0x3ff0300f 22*4882a593SmuzhiyunDATA 4, CCM_CCGR4, 0xfffff300 23*4882a593SmuzhiyunDATA 4, CCM_CCGR5, 0x0f0000c3 24*4882a593SmuzhiyunDATA 4, CCM_CCGR6, 0x00000fff 25