1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Altera SoCFPGA Clock and PLL configuration 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: BSD-3-Clause 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __SOCFPGA_PLL_CONFIG_H__ 8*4882a593Smuzhiyun #define __SOCFPGA_PLL_CONFIG_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CONFIG_HPS_DBCTRL_STAYOSC1 1 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 13*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 14*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 15*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 16*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 17*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 18*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 19*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 20*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 21*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 22*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 23*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 24*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 25*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 26*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 27*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 28*4882a593Smuzhiyun #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 31*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 32*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 33*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 34*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 35*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 36*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 37*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 38*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 39*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 40*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 41*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 42*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 43*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 44*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 45*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 46*4882a593Smuzhiyun #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 49*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 50*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 51*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 52*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 53*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 54*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 55*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 56*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 57*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 58*4882a593Smuzhiyun #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_HPS_CLK_OSC1_HZ 25000000 61*4882a593Smuzhiyun #define CONFIG_HPS_CLK_OSC2_HZ 25000000 62*4882a593Smuzhiyun #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 63*4882a593Smuzhiyun #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 64*4882a593Smuzhiyun #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 65*4882a593Smuzhiyun #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 66*4882a593Smuzhiyun #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 67*4882a593Smuzhiyun #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 68*4882a593Smuzhiyun #define CONFIG_HPS_CLK_EMAC1_HZ 1953125 69*4882a593Smuzhiyun #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 70*4882a593Smuzhiyun #define CONFIG_HPS_CLK_NAND_HZ 50000000 71*4882a593Smuzhiyun #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 72*4882a593Smuzhiyun #define CONFIG_HPS_CLK_QSPI_HZ 3125000 73*4882a593Smuzhiyun #define CONFIG_HPS_CLK_SPIM_HZ 200000000 74*4882a593Smuzhiyun #define CONFIG_HPS_CLK_CAN0_HZ 100000000 75*4882a593Smuzhiyun #define CONFIG_HPS_CLK_CAN1_HZ 100000000 76*4882a593Smuzhiyun #define CONFIG_HPS_CLK_GPIODB_HZ 32000 77*4882a593Smuzhiyun #define CONFIG_HPS_CLK_L4_MP_HZ 100000000 78*4882a593Smuzhiyun #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 81*4882a593Smuzhiyun #define CONFIG_HPS_ALTERAGRP_MAINCLK 3 82*4882a593Smuzhiyun #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* __SOCFPGA_PLL_CONFIG_H__ */ 86