1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Amazon Kindle Fire (first generation) codename kc1 config 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _KC1_H_ 10*4882a593Smuzhiyun #define _KC1_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/arch/mux_omap4.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define KC1_GPIO_USB_ID 52 15*4882a593Smuzhiyun #define KC1_GPIO_MBID1 173 16*4882a593Smuzhiyun #define KC1_GPIO_MBID0 174 17*4882a593Smuzhiyun #define KC1_GPIO_MBID3 177 18*4882a593Smuzhiyun #define KC1_GPIO_MBID2 178 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun const struct pad_conf_entry core_padconf_array[] = { 21*4882a593Smuzhiyun /* GPMC */ 22*4882a593Smuzhiyun { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */ 23*4882a593Smuzhiyun { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */ 24*4882a593Smuzhiyun { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */ 25*4882a593Smuzhiyun { GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */ 26*4882a593Smuzhiyun { GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */ 27*4882a593Smuzhiyun { GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */ 28*4882a593Smuzhiyun { GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */ 29*4882a593Smuzhiyun { GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */ 30*4882a593Smuzhiyun { GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */ 31*4882a593Smuzhiyun { GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */ 32*4882a593Smuzhiyun { GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */ 33*4882a593Smuzhiyun /* CAM */ 34*4882a593Smuzhiyun { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */ 35*4882a593Smuzhiyun { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */ 36*4882a593Smuzhiyun { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */ 37*4882a593Smuzhiyun /* HDQ */ 38*4882a593Smuzhiyun { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */ 39*4882a593Smuzhiyun /* I2C1 */ 40*4882a593Smuzhiyun { I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */ 41*4882a593Smuzhiyun { I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */ 42*4882a593Smuzhiyun /* I2C2 */ 43*4882a593Smuzhiyun { I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */ 44*4882a593Smuzhiyun { I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */ 45*4882a593Smuzhiyun /* I2C3 */ 46*4882a593Smuzhiyun { I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */ 47*4882a593Smuzhiyun { I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */ 48*4882a593Smuzhiyun /* I2C4 */ 49*4882a593Smuzhiyun { I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */ 50*4882a593Smuzhiyun { I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */ 51*4882a593Smuzhiyun /* MCSPI1 */ 52*4882a593Smuzhiyun { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */ 53*4882a593Smuzhiyun { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */ 54*4882a593Smuzhiyun { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */ 55*4882a593Smuzhiyun { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */ 56*4882a593Smuzhiyun { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */ 57*4882a593Smuzhiyun { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */ 58*4882a593Smuzhiyun { MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */ 59*4882a593Smuzhiyun /* UART3 */ 60*4882a593Smuzhiyun { UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */ 61*4882a593Smuzhiyun { UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */ 62*4882a593Smuzhiyun { UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */ 63*4882a593Smuzhiyun { UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */ 64*4882a593Smuzhiyun /* SDMMC5 */ 65*4882a593Smuzhiyun { SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */ 66*4882a593Smuzhiyun { SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */ 67*4882a593Smuzhiyun { SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */ 68*4882a593Smuzhiyun { SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */ 69*4882a593Smuzhiyun { SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */ 70*4882a593Smuzhiyun { SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */ 71*4882a593Smuzhiyun /* MCSPI4 */ 72*4882a593Smuzhiyun { MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */ 73*4882a593Smuzhiyun { MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */ 74*4882a593Smuzhiyun { MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */ 75*4882a593Smuzhiyun { MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */ 76*4882a593Smuzhiyun /* UART4 */ 77*4882a593Smuzhiyun { UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */ 78*4882a593Smuzhiyun { UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */ 79*4882a593Smuzhiyun /* UNIPRO */ 80*4882a593Smuzhiyun { UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */ 81*4882a593Smuzhiyun { UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */ 82*4882a593Smuzhiyun { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */ 83*4882a593Smuzhiyun { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */ 84*4882a593Smuzhiyun { UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */ 85*4882a593Smuzhiyun { UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */ 86*4882a593Smuzhiyun { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */ 87*4882a593Smuzhiyun { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */ 88*4882a593Smuzhiyun { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */ 89*4882a593Smuzhiyun { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */ 90*4882a593Smuzhiyun { UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */ 91*4882a593Smuzhiyun { UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */ 92*4882a593Smuzhiyun /* USBA0_OTG */ 93*4882a593Smuzhiyun { USBA0_OTG_CE, (IDIS | PTD | M0) }, /* usba0_otg_ce */ 94*4882a593Smuzhiyun { USBA0_OTG_DP, (IEN | DIS | M0) }, /* usba0_otg_dp */ 95*4882a593Smuzhiyun { USBA0_OTG_DM, (IEN | DIS | M0) }, /* usba0_otg_dm */ 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif 99