1 /*
2 * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
3 *
4 * Based on sheevaplug.c originally written by
5 * Prafulla Wadaskar <prafulla@marvell.com>
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <common.h>
13 #include <miiphy.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/mpp.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/io.h>
18 #include <asm/mach-types.h>
19 #include "dockstar.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
board_early_init_f(void)23 int board_early_init_f(void)
24 {
25 /*
26 * default gpio configuration
27 * There are maximum 64 gpios controlled through 2 sets of registers
28 * the below configuration configures mainly initial LED status
29 */
30 mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
31 DOCKSTAR_OE_VAL_HIGH,
32 DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
33
34 /* Multi-Purpose Pins Functionality configuration */
35 static const u32 kwmpp_config[] = {
36 MPP0_NF_IO2,
37 MPP1_NF_IO3,
38 MPP2_NF_IO4,
39 MPP3_NF_IO5,
40 MPP4_NF_IO6,
41 MPP5_NF_IO7,
42 MPP6_SYSRST_OUTn,
43 MPP7_GPO,
44 MPP8_UART0_RTS,
45 MPP9_UART0_CTS,
46 MPP10_UART0_TXD,
47 MPP11_UART0_RXD,
48 MPP12_SD_CLK,
49 MPP13_SD_CMD,
50 MPP14_SD_D0,
51 MPP15_SD_D1,
52 MPP16_SD_D2,
53 MPP17_SD_D3,
54 MPP18_NF_IO0,
55 MPP19_NF_IO1,
56 MPP20_GPIO,
57 MPP21_GPIO,
58 MPP22_GPIO,
59 MPP23_GPIO,
60 MPP24_GPIO,
61 MPP25_GPIO,
62 MPP26_GPIO,
63 MPP27_GPIO,
64 MPP28_GPIO,
65 MPP29_TSMP9,
66 MPP30_GPIO,
67 MPP31_GPIO,
68 MPP32_GPIO,
69 MPP33_GPIO,
70 MPP34_GPIO,
71 MPP35_GPIO,
72 MPP36_GPIO,
73 MPP37_GPIO,
74 MPP38_GPIO,
75 MPP39_GPIO,
76 MPP40_GPIO,
77 MPP41_GPIO,
78 MPP42_GPIO,
79 MPP43_GPIO,
80 MPP44_GPIO,
81 MPP45_GPIO,
82 MPP46_GPIO,
83 MPP47_GPIO,
84 MPP48_GPIO,
85 MPP49_GPIO,
86 0
87 };
88 kirkwood_mpp_conf(kwmpp_config, NULL);
89 return 0;
90 }
91
board_init(void)92 int board_init(void)
93 {
94 /*
95 * arch number of board
96 */
97 gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
98
99 /* address of boot parameters */
100 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
101
102 return 0;
103 }
104
105 #ifdef CONFIG_RESET_PHY_R
106 /* Configure and enable MV88E1116 PHY */
reset_phy(void)107 void reset_phy(void)
108 {
109 u16 reg;
110 u16 devadr;
111 char *name = "egiga0";
112
113 if (miiphy_set_current_dev(name))
114 return;
115
116 /* command to read PHY dev address */
117 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
118 printf("Err..%s could not read PHY dev address\n",
119 __FUNCTION__);
120 return;
121 }
122
123 /*
124 * Enable RGMII delay on Tx and Rx for CPU port
125 * Ref: sec 4.7.2 of chip datasheet
126 */
127 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
128 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
129 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
130 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
131 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
132
133 /* reset the phy */
134 miiphy_reset(name, devadr);
135
136 printf("88E1116 Initialized on %s\n", name);
137 }
138 #endif /* CONFIG_RESET_PHY_R */
139
140 #define GREEN_LED (1 << 14)
141 #define ORANGE_LED (1 << 15)
142 #define BOTH_LEDS (GREEN_LED | ORANGE_LED)
143 #define NEITHER_LED 0
144
set_leds(u32 leds,u32 blinking)145 static void set_leds(u32 leds, u32 blinking)
146 {
147 struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
148 u32 oe = readl(&r->oe) | BOTH_LEDS;
149 writel(oe & ~leds, &r->oe); /* active low */
150 u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
151 writel(bl | blinking, &r->blink_en);
152 }
153
show_boot_progress(int val)154 void show_boot_progress(int val)
155 {
156 switch (val) {
157 case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
158 set_leds(BOTH_LEDS, NEITHER_LED);
159 break;
160 case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
161 set_leds(GREEN_LED, GREEN_LED);
162 break;
163 default:
164 if (val < 0) /* error */
165 set_leds(ORANGE_LED, ORANGE_LED);
166 break;
167 }
168 }
169