1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Based on sheevaplug.c originally written by
5*4882a593Smuzhiyun * Prafulla Wadaskar <prafulla@marvell.com>
6*4882a593Smuzhiyun * (C) Copyright 2009
7*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <miiphy.h>
14*4882a593Smuzhiyun #include <asm/arch/soc.h>
15*4882a593Smuzhiyun #include <asm/arch/mpp.h>
16*4882a593Smuzhiyun #include <asm/arch/cpu.h>
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun #include <asm/mach-types.h>
19*4882a593Smuzhiyun #include "dockstar.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
22*4882a593Smuzhiyun
board_early_init_f(void)23*4882a593Smuzhiyun int board_early_init_f(void)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * default gpio configuration
27*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
28*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
31*4882a593Smuzhiyun DOCKSTAR_OE_VAL_HIGH,
32*4882a593Smuzhiyun DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
35*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
36*4882a593Smuzhiyun MPP0_NF_IO2,
37*4882a593Smuzhiyun MPP1_NF_IO3,
38*4882a593Smuzhiyun MPP2_NF_IO4,
39*4882a593Smuzhiyun MPP3_NF_IO5,
40*4882a593Smuzhiyun MPP4_NF_IO6,
41*4882a593Smuzhiyun MPP5_NF_IO7,
42*4882a593Smuzhiyun MPP6_SYSRST_OUTn,
43*4882a593Smuzhiyun MPP7_GPO,
44*4882a593Smuzhiyun MPP8_UART0_RTS,
45*4882a593Smuzhiyun MPP9_UART0_CTS,
46*4882a593Smuzhiyun MPP10_UART0_TXD,
47*4882a593Smuzhiyun MPP11_UART0_RXD,
48*4882a593Smuzhiyun MPP12_SD_CLK,
49*4882a593Smuzhiyun MPP13_SD_CMD,
50*4882a593Smuzhiyun MPP14_SD_D0,
51*4882a593Smuzhiyun MPP15_SD_D1,
52*4882a593Smuzhiyun MPP16_SD_D2,
53*4882a593Smuzhiyun MPP17_SD_D3,
54*4882a593Smuzhiyun MPP18_NF_IO0,
55*4882a593Smuzhiyun MPP19_NF_IO1,
56*4882a593Smuzhiyun MPP20_GPIO,
57*4882a593Smuzhiyun MPP21_GPIO,
58*4882a593Smuzhiyun MPP22_GPIO,
59*4882a593Smuzhiyun MPP23_GPIO,
60*4882a593Smuzhiyun MPP24_GPIO,
61*4882a593Smuzhiyun MPP25_GPIO,
62*4882a593Smuzhiyun MPP26_GPIO,
63*4882a593Smuzhiyun MPP27_GPIO,
64*4882a593Smuzhiyun MPP28_GPIO,
65*4882a593Smuzhiyun MPP29_TSMP9,
66*4882a593Smuzhiyun MPP30_GPIO,
67*4882a593Smuzhiyun MPP31_GPIO,
68*4882a593Smuzhiyun MPP32_GPIO,
69*4882a593Smuzhiyun MPP33_GPIO,
70*4882a593Smuzhiyun MPP34_GPIO,
71*4882a593Smuzhiyun MPP35_GPIO,
72*4882a593Smuzhiyun MPP36_GPIO,
73*4882a593Smuzhiyun MPP37_GPIO,
74*4882a593Smuzhiyun MPP38_GPIO,
75*4882a593Smuzhiyun MPP39_GPIO,
76*4882a593Smuzhiyun MPP40_GPIO,
77*4882a593Smuzhiyun MPP41_GPIO,
78*4882a593Smuzhiyun MPP42_GPIO,
79*4882a593Smuzhiyun MPP43_GPIO,
80*4882a593Smuzhiyun MPP44_GPIO,
81*4882a593Smuzhiyun MPP45_GPIO,
82*4882a593Smuzhiyun MPP46_GPIO,
83*4882a593Smuzhiyun MPP47_GPIO,
84*4882a593Smuzhiyun MPP48_GPIO,
85*4882a593Smuzhiyun MPP49_GPIO,
86*4882a593Smuzhiyun 0
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
board_init(void)92*4882a593Smuzhiyun int board_init(void)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun /*
95*4882a593Smuzhiyun * arch number of board
96*4882a593Smuzhiyun */
97*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* address of boot parameters */
100*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #ifdef CONFIG_RESET_PHY_R
106*4882a593Smuzhiyun /* Configure and enable MV88E1116 PHY */
reset_phy(void)107*4882a593Smuzhiyun void reset_phy(void)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun u16 reg;
110*4882a593Smuzhiyun u16 devadr;
111*4882a593Smuzhiyun char *name = "egiga0";
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (miiphy_set_current_dev(name))
114*4882a593Smuzhiyun return;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* command to read PHY dev address */
117*4882a593Smuzhiyun if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
118*4882a593Smuzhiyun printf("Err..%s could not read PHY dev address\n",
119*4882a593Smuzhiyun __FUNCTION__);
120*4882a593Smuzhiyun return;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /*
124*4882a593Smuzhiyun * Enable RGMII delay on Tx and Rx for CPU port
125*4882a593Smuzhiyun * Ref: sec 4.7.2 of chip datasheet
126*4882a593Smuzhiyun */
127*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
128*4882a593Smuzhiyun miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
129*4882a593Smuzhiyun reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
130*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
131*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* reset the phy */
134*4882a593Smuzhiyun miiphy_reset(name, devadr);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun printf("88E1116 Initialized on %s\n", name);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun #endif /* CONFIG_RESET_PHY_R */
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #define GREEN_LED (1 << 14)
141*4882a593Smuzhiyun #define ORANGE_LED (1 << 15)
142*4882a593Smuzhiyun #define BOTH_LEDS (GREEN_LED | ORANGE_LED)
143*4882a593Smuzhiyun #define NEITHER_LED 0
144*4882a593Smuzhiyun
set_leds(u32 leds,u32 blinking)145*4882a593Smuzhiyun static void set_leds(u32 leds, u32 blinking)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
148*4882a593Smuzhiyun u32 oe = readl(&r->oe) | BOTH_LEDS;
149*4882a593Smuzhiyun writel(oe & ~leds, &r->oe); /* active low */
150*4882a593Smuzhiyun u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
151*4882a593Smuzhiyun writel(bl | blinking, &r->blink_en);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
show_boot_progress(int val)154*4882a593Smuzhiyun void show_boot_progress(int val)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun switch (val) {
157*4882a593Smuzhiyun case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
158*4882a593Smuzhiyun set_leds(BOTH_LEDS, NEITHER_LED);
159*4882a593Smuzhiyun break;
160*4882a593Smuzhiyun case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
161*4882a593Smuzhiyun set_leds(GREEN_LED, GREEN_LED);
162*4882a593Smuzhiyun break;
163*4882a593Smuzhiyun default:
164*4882a593Smuzhiyun if (val < 0) /* error */
165*4882a593Smuzhiyun set_leds(ORANGE_LED, ORANGE_LED);
166*4882a593Smuzhiyun break;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169