1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009
3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <miiphy.h>
11*4882a593Smuzhiyun #include <asm/mach-types.h>
12*4882a593Smuzhiyun #include <asm/arch/cpu.h>
13*4882a593Smuzhiyun #include <asm/arch/soc.h>
14*4882a593Smuzhiyun #include <asm/arch/mpp.h>
15*4882a593Smuzhiyun #include "sheevaplug.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
board_early_init_f(void)19*4882a593Smuzhiyun int board_early_init_f(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * default gpio configuration
23*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
24*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
27*4882a593Smuzhiyun SHEEVAPLUG_OE_VAL_HIGH,
28*4882a593Smuzhiyun SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
31*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
32*4882a593Smuzhiyun MPP0_NF_IO2,
33*4882a593Smuzhiyun MPP1_NF_IO3,
34*4882a593Smuzhiyun MPP2_NF_IO4,
35*4882a593Smuzhiyun MPP3_NF_IO5,
36*4882a593Smuzhiyun MPP4_NF_IO6,
37*4882a593Smuzhiyun MPP5_NF_IO7,
38*4882a593Smuzhiyun MPP6_SYSRST_OUTn,
39*4882a593Smuzhiyun MPP7_GPO,
40*4882a593Smuzhiyun MPP8_UART0_RTS,
41*4882a593Smuzhiyun MPP9_UART0_CTS,
42*4882a593Smuzhiyun MPP10_UART0_TXD,
43*4882a593Smuzhiyun MPP11_UART0_RXD,
44*4882a593Smuzhiyun MPP12_SD_CLK,
45*4882a593Smuzhiyun MPP13_SD_CMD,
46*4882a593Smuzhiyun MPP14_SD_D0,
47*4882a593Smuzhiyun MPP15_SD_D1,
48*4882a593Smuzhiyun MPP16_SD_D2,
49*4882a593Smuzhiyun MPP17_SD_D3,
50*4882a593Smuzhiyun MPP18_NF_IO0,
51*4882a593Smuzhiyun MPP19_NF_IO1,
52*4882a593Smuzhiyun MPP20_GPIO,
53*4882a593Smuzhiyun MPP21_GPIO,
54*4882a593Smuzhiyun MPP22_GPIO,
55*4882a593Smuzhiyun MPP23_GPIO,
56*4882a593Smuzhiyun MPP24_GPIO,
57*4882a593Smuzhiyun MPP25_GPIO,
58*4882a593Smuzhiyun MPP26_GPIO,
59*4882a593Smuzhiyun MPP27_GPIO,
60*4882a593Smuzhiyun MPP28_GPIO,
61*4882a593Smuzhiyun MPP29_TSMP9,
62*4882a593Smuzhiyun MPP30_GPIO,
63*4882a593Smuzhiyun MPP31_GPIO,
64*4882a593Smuzhiyun MPP32_GPIO,
65*4882a593Smuzhiyun MPP33_GPIO,
66*4882a593Smuzhiyun MPP34_GPIO,
67*4882a593Smuzhiyun MPP35_GPIO,
68*4882a593Smuzhiyun MPP36_GPIO,
69*4882a593Smuzhiyun MPP37_GPIO,
70*4882a593Smuzhiyun MPP38_GPIO,
71*4882a593Smuzhiyun MPP39_GPIO,
72*4882a593Smuzhiyun MPP40_GPIO,
73*4882a593Smuzhiyun MPP41_GPIO,
74*4882a593Smuzhiyun MPP42_GPIO,
75*4882a593Smuzhiyun MPP43_GPIO,
76*4882a593Smuzhiyun MPP44_GPIO,
77*4882a593Smuzhiyun MPP45_GPIO,
78*4882a593Smuzhiyun MPP46_GPIO,
79*4882a593Smuzhiyun MPP47_GPIO,
80*4882a593Smuzhiyun MPP48_GPIO,
81*4882a593Smuzhiyun MPP49_GPIO,
82*4882a593Smuzhiyun 0
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
board_init(void)88*4882a593Smuzhiyun int board_init(void)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * arch number of board
92*4882a593Smuzhiyun */
93*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* adress of boot parameters */
96*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #ifdef CONFIG_RESET_PHY_R
102*4882a593Smuzhiyun /* Configure and enable MV88E1116 PHY */
reset_phy(void)103*4882a593Smuzhiyun void reset_phy(void)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun u16 reg;
106*4882a593Smuzhiyun u16 devadr;
107*4882a593Smuzhiyun char *name = "egiga0";
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (miiphy_set_current_dev(name))
110*4882a593Smuzhiyun return;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* command to read PHY dev address */
113*4882a593Smuzhiyun if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
114*4882a593Smuzhiyun printf("Err..%s could not read PHY dev address\n",
115*4882a593Smuzhiyun __FUNCTION__);
116*4882a593Smuzhiyun return;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun * Enable RGMII delay on Tx and Rx for CPU port
121*4882a593Smuzhiyun * Ref: sec 4.7.2 of chip datasheet
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
124*4882a593Smuzhiyun miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
125*4882a593Smuzhiyun reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
126*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
127*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* reset the phy */
130*4882a593Smuzhiyun miiphy_reset(name, devadr);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun printf("88E1116 Initialized on %s\n", name);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun #endif /* CONFIG_RESET_PHY_R */
135