1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009
3*4882a593Smuzhiyun * Net Insight <www.netinsight.net>
4*4882a593Smuzhiyun * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on sheevaplug.c:
7*4882a593Smuzhiyun * (C) Copyright 2009
8*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
9*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <common.h>
15*4882a593Smuzhiyun #include <miiphy.h>
16*4882a593Smuzhiyun #include <asm/mach-types.h>
17*4882a593Smuzhiyun #include <asm/arch/cpu.h>
18*4882a593Smuzhiyun #include <asm/arch/soc.h>
19*4882a593Smuzhiyun #include <asm/arch/mpp.h>
20*4882a593Smuzhiyun #include "openrd.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
23*4882a593Smuzhiyun
board_early_init_f(void)24*4882a593Smuzhiyun int board_early_init_f(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * default gpio configuration
28*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
29*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun mvebu_config_gpio(OPENRD_OE_VAL_LOW,
32*4882a593Smuzhiyun OPENRD_OE_VAL_HIGH,
33*4882a593Smuzhiyun OPENRD_OE_LOW, OPENRD_OE_HIGH);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
36*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
37*4882a593Smuzhiyun MPP0_NF_IO2,
38*4882a593Smuzhiyun MPP1_NF_IO3,
39*4882a593Smuzhiyun MPP2_NF_IO4,
40*4882a593Smuzhiyun MPP3_NF_IO5,
41*4882a593Smuzhiyun MPP4_NF_IO6,
42*4882a593Smuzhiyun MPP5_NF_IO7,
43*4882a593Smuzhiyun MPP6_SYSRST_OUTn,
44*4882a593Smuzhiyun MPP7_GPO,
45*4882a593Smuzhiyun MPP8_TW_SDA,
46*4882a593Smuzhiyun MPP9_TW_SCK,
47*4882a593Smuzhiyun MPP10_UART0_TXD,
48*4882a593Smuzhiyun MPP11_UART0_RXD,
49*4882a593Smuzhiyun MPP12_SD_CLK,
50*4882a593Smuzhiyun MPP13_SD_CMD, /* Alt UART1_TXD */
51*4882a593Smuzhiyun MPP14_SD_D0, /* Alt UART1_RXD */
52*4882a593Smuzhiyun MPP15_SD_D1,
53*4882a593Smuzhiyun MPP16_SD_D2,
54*4882a593Smuzhiyun MPP17_SD_D3,
55*4882a593Smuzhiyun MPP18_NF_IO0,
56*4882a593Smuzhiyun MPP19_NF_IO1,
57*4882a593Smuzhiyun MPP20_GE1_0,
58*4882a593Smuzhiyun MPP21_GE1_1,
59*4882a593Smuzhiyun MPP22_GE1_2,
60*4882a593Smuzhiyun MPP23_GE1_3,
61*4882a593Smuzhiyun MPP24_GE1_4,
62*4882a593Smuzhiyun MPP25_GE1_5,
63*4882a593Smuzhiyun MPP26_GE1_6,
64*4882a593Smuzhiyun MPP27_GE1_7,
65*4882a593Smuzhiyun MPP28_GPIO,
66*4882a593Smuzhiyun MPP29_TSMP9,
67*4882a593Smuzhiyun MPP30_GE1_10,
68*4882a593Smuzhiyun MPP31_GE1_11,
69*4882a593Smuzhiyun MPP32_GE1_12,
70*4882a593Smuzhiyun MPP33_GE1_13,
71*4882a593Smuzhiyun MPP34_GPIO, /* UART1 / SD sel */
72*4882a593Smuzhiyun MPP35_TDM_CH0_TX_QL,
73*4882a593Smuzhiyun MPP36_TDM_SPI_CS1,
74*4882a593Smuzhiyun MPP37_TDM_CH2_TX_QL,
75*4882a593Smuzhiyun MPP38_TDM_CH2_RX_QL,
76*4882a593Smuzhiyun MPP39_AUDIO_I2SBCLK,
77*4882a593Smuzhiyun MPP40_AUDIO_I2SDO,
78*4882a593Smuzhiyun MPP41_AUDIO_I2SLRC,
79*4882a593Smuzhiyun MPP42_AUDIO_I2SMCLK,
80*4882a593Smuzhiyun MPP43_AUDIO_I2SDI,
81*4882a593Smuzhiyun MPP44_AUDIO_EXTCLK,
82*4882a593Smuzhiyun MPP45_TDM_PCLK,
83*4882a593Smuzhiyun MPP46_TDM_FS,
84*4882a593Smuzhiyun MPP47_TDM_DRX,
85*4882a593Smuzhiyun MPP48_TDM_DTX,
86*4882a593Smuzhiyun MPP49_TDM_CH0_RX_QL,
87*4882a593Smuzhiyun 0
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
board_init(void)94*4882a593Smuzhiyun int board_init(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * arch number of board
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun #if defined(CONFIG_BOARD_IS_OPENRD_BASE)
100*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
101*4882a593Smuzhiyun #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
102*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
103*4882a593Smuzhiyun #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
104*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
105*4882a593Smuzhiyun #endif
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* adress of boot parameters */
108*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #ifdef CONFIG_RESET_PHY_R
113*4882a593Smuzhiyun /* Configure and enable MV88E1116/88E1121 PHY */
mv_phy_init(char * name)114*4882a593Smuzhiyun void mv_phy_init(char *name)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun u16 reg;
117*4882a593Smuzhiyun u16 devadr;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (miiphy_set_current_dev(name))
120*4882a593Smuzhiyun return;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* command to read PHY dev address */
123*4882a593Smuzhiyun if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
124*4882a593Smuzhiyun printf("Err..%s could not read PHY dev address\n", __func__);
125*4882a593Smuzhiyun return;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /*
129*4882a593Smuzhiyun * Enable RGMII delay on Tx and Rx for CPU port
130*4882a593Smuzhiyun * Ref: sec 4.7.2 of chip datasheet
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
133*4882a593Smuzhiyun miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
134*4882a593Smuzhiyun reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
135*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
136*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* reset the phy */
139*4882a593Smuzhiyun miiphy_reset(name, devadr);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun printf(PHY_NO" Initialized on %s\n", name);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
reset_phy(void)144*4882a593Smuzhiyun void reset_phy(void)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun mv_phy_init("egiga0");
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
149*4882a593Smuzhiyun /* Kirkwood ethernet driver is written with the assumption that in case
150*4882a593Smuzhiyun * of multiple PHYs, their addresses are consecutive. But unfortunately
151*4882a593Smuzhiyun * in case of OpenRD-Client, PHY addresses are not consecutive.*/
152*4882a593Smuzhiyun miiphy_write("egiga1", 0xEE, 0xEE, 24);
153*4882a593Smuzhiyun #endif
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
156*4882a593Smuzhiyun defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
157*4882a593Smuzhiyun /* configure and initialize both PHY's */
158*4882a593Smuzhiyun mv_phy_init("egiga1");
159*4882a593Smuzhiyun #endif
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun #endif /* CONFIG_RESET_PHY_R */
162