1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2011
3*4882a593Smuzhiyun * Jason Cooper <u-boot@lakedaemon.net>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on work by:
6*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
7*4882a593Smuzhiyun * Written-by: Siddarth Gore <gores@marvell.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <miiphy.h>
14*4882a593Smuzhiyun #include <asm/arch/cpu.h>
15*4882a593Smuzhiyun #include <asm/arch/soc.h>
16*4882a593Smuzhiyun #include <asm/arch/mpp.h>
17*4882a593Smuzhiyun #include "dreamplug.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
board_early_init_f(void)21*4882a593Smuzhiyun int board_early_init_f(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * default gpio configuration
25*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
26*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
29*4882a593Smuzhiyun DREAMPLUG_OE_VAL_HIGH,
30*4882a593Smuzhiyun DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
33*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
34*4882a593Smuzhiyun MPP0_SPI_SCn, /* SPI Flash */
35*4882a593Smuzhiyun MPP1_SPI_MOSI,
36*4882a593Smuzhiyun MPP2_SPI_SCK,
37*4882a593Smuzhiyun MPP3_SPI_MISO,
38*4882a593Smuzhiyun MPP4_NF_IO6,
39*4882a593Smuzhiyun MPP5_NF_IO7,
40*4882a593Smuzhiyun MPP6_SYSRST_OUTn,
41*4882a593Smuzhiyun MPP7_GPO,
42*4882a593Smuzhiyun MPP8_TW_SDA,
43*4882a593Smuzhiyun MPP9_TW_SCK,
44*4882a593Smuzhiyun MPP10_UART0_TXD, /* Serial */
45*4882a593Smuzhiyun MPP11_UART0_RXD,
46*4882a593Smuzhiyun MPP12_SD_CLK, /* SDIO Slot */
47*4882a593Smuzhiyun MPP13_SD_CMD,
48*4882a593Smuzhiyun MPP14_SD_D0,
49*4882a593Smuzhiyun MPP15_SD_D1,
50*4882a593Smuzhiyun MPP16_SD_D2,
51*4882a593Smuzhiyun MPP17_SD_D3,
52*4882a593Smuzhiyun MPP18_NF_IO0,
53*4882a593Smuzhiyun MPP19_NF_IO1,
54*4882a593Smuzhiyun MPP20_GE1_0, /* Gigabit Ethernet */
55*4882a593Smuzhiyun MPP21_GE1_1,
56*4882a593Smuzhiyun MPP22_GE1_2,
57*4882a593Smuzhiyun MPP23_GE1_3,
58*4882a593Smuzhiyun MPP24_GE1_4,
59*4882a593Smuzhiyun MPP25_GE1_5,
60*4882a593Smuzhiyun MPP26_GE1_6,
61*4882a593Smuzhiyun MPP27_GE1_7,
62*4882a593Smuzhiyun MPP28_GE1_8,
63*4882a593Smuzhiyun MPP29_GE1_9,
64*4882a593Smuzhiyun MPP30_GE1_10,
65*4882a593Smuzhiyun MPP31_GE1_11,
66*4882a593Smuzhiyun MPP32_GE1_12,
67*4882a593Smuzhiyun MPP33_GE1_13,
68*4882a593Smuzhiyun MPP34_GE1_14,
69*4882a593Smuzhiyun MPP35_GE1_15,
70*4882a593Smuzhiyun MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
71*4882a593Smuzhiyun MPP37_GPIO,
72*4882a593Smuzhiyun MPP38_GPIO,
73*4882a593Smuzhiyun MPP39_GPIO,
74*4882a593Smuzhiyun MPP40_TDM_SPI_SCK,
75*4882a593Smuzhiyun MPP41_TDM_SPI_MISO,
76*4882a593Smuzhiyun MPP42_TDM_SPI_MOSI,
77*4882a593Smuzhiyun MPP43_GPIO,
78*4882a593Smuzhiyun MPP44_GPIO,
79*4882a593Smuzhiyun MPP45_GPIO,
80*4882a593Smuzhiyun MPP46_GPIO,
81*4882a593Smuzhiyun MPP47_GPIO, /* Bluetooth LED */
82*4882a593Smuzhiyun MPP48_GPIO, /* Wifi LED */
83*4882a593Smuzhiyun MPP49_GPIO, /* Wifi AP LED */
84*4882a593Smuzhiyun 0
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
board_init(void)90*4882a593Smuzhiyun int board_init(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun /* adress of boot parameters */
93*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #ifdef CONFIG_RESET_PHY_R
mv_phy_88e1116_init(char * name)99*4882a593Smuzhiyun void mv_phy_88e1116_init(char *name)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun u16 reg;
102*4882a593Smuzhiyun u16 devadr;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (miiphy_set_current_dev(name))
105*4882a593Smuzhiyun return;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* command to read PHY dev address */
108*4882a593Smuzhiyun if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
109*4882a593Smuzhiyun printf("Err..%s could not read PHY dev address\n",
110*4882a593Smuzhiyun __func__);
111*4882a593Smuzhiyun return;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * Enable RGMII delay on Tx and Rx for CPU port
116*4882a593Smuzhiyun * Ref: sec 4.7.2 of chip datasheet
117*4882a593Smuzhiyun */
118*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
119*4882a593Smuzhiyun miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
120*4882a593Smuzhiyun reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
121*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
122*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* reset the phy */
125*4882a593Smuzhiyun miiphy_reset(name, devadr);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun printf("88E1116 Initialized on %s\n", name);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
reset_phy(void)130*4882a593Smuzhiyun void reset_phy(void)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun /* configure and initialize both PHY's */
133*4882a593Smuzhiyun mv_phy_88e1116_init("egiga0");
134*4882a593Smuzhiyun mv_phy_88e1116_init("egiga1");
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun #endif /* CONFIG_RESET_PHY_R */
137