1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <miiphy.h>
9*4882a593Smuzhiyun #include <netdev.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/cpu.h>
12*4882a593Smuzhiyun #include <asm/arch/soc.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * Those values and defines are taken from the Marvell U-Boot version
18*4882a593Smuzhiyun * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun #define DB_88F6720_MPP0_7 0x00020020 /* SPI */
21*4882a593Smuzhiyun #define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
22*4882a593Smuzhiyun #define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
23*4882a593Smuzhiyun #define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
24*4882a593Smuzhiyun #define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
25*4882a593Smuzhiyun #define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
26*4882a593Smuzhiyun #define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
27*4882a593Smuzhiyun #define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
28*4882a593Smuzhiyun #define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
31*4882a593Smuzhiyun #define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
32*4882a593Smuzhiyun #define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
33*4882a593Smuzhiyun #define DB_88F6720_GPP_OUT_VAL_LOW 0x0
34*4882a593Smuzhiyun #define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
35*4882a593Smuzhiyun #define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
36*4882a593Smuzhiyun #define DB_88F6720_GPP_POL_LOW 0x0
37*4882a593Smuzhiyun #define DB_88F6720_GPP_POL_MID 0x0
38*4882a593Smuzhiyun #define DB_88F6720_GPP_POL_HIGH 0x0
39*4882a593Smuzhiyun
board_early_init_f(void)40*4882a593Smuzhiyun int board_early_init_f(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun /* Configure MPP */
43*4882a593Smuzhiyun writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
44*4882a593Smuzhiyun writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
45*4882a593Smuzhiyun writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
46*4882a593Smuzhiyun writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
47*4882a593Smuzhiyun writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
48*4882a593Smuzhiyun writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
49*4882a593Smuzhiyun writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
50*4882a593Smuzhiyun writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
51*4882a593Smuzhiyun writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Configure GPIO */
54*4882a593Smuzhiyun /* Set GPP Out value */
55*4882a593Smuzhiyun writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
56*4882a593Smuzhiyun writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
57*4882a593Smuzhiyun writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Set GPP Polarity */
60*4882a593Smuzhiyun writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
61*4882a593Smuzhiyun writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
62*4882a593Smuzhiyun writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Set GPP Out Enable */
65*4882a593Smuzhiyun writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
66*4882a593Smuzhiyun writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
67*4882a593Smuzhiyun writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
board_init(void)72*4882a593Smuzhiyun int board_init(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun /* adress of boot parameters */
75*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
checkboard(void)80*4882a593Smuzhiyun int checkboard(void)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun puts("Board: Marvell DB-88F6720\n");
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
board_eth_init(bd_t * bis)87*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun cpu_eth_init(bis); /* Built in controller(s) come first */
90*4882a593Smuzhiyun return pci_eth_init(bis);
91*4882a593Smuzhiyun }
92