xref: /OK3568_Linux_fs/u-boot/board/Barix/ipam390/ipam390.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
3*4882a593Smuzhiyun  * Based on:
4*4882a593Smuzhiyun  * U-Boot:board/davinci/da8xxevm/da850evm.c
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Based on da830evm.c. Original Copyrights follow:
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
11*4882a593Smuzhiyun  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <common.h>
17*4882a593Smuzhiyun #include <i2c.h>
18*4882a593Smuzhiyun #include <net.h>
19*4882a593Smuzhiyun #include <netdev.h>
20*4882a593Smuzhiyun #include <spi.h>
21*4882a593Smuzhiyun #include <spi_flash.h>
22*4882a593Smuzhiyun #include <asm/arch/hardware.h>
23*4882a593Smuzhiyun #include <asm/ti-common/davinci_nand.h>
24*4882a593Smuzhiyun #include <asm/arch/emac_defs.h>
25*4882a593Smuzhiyun #include <asm/arch/pinmux_defs.h>
26*4882a593Smuzhiyun #include <asm/io.h>
27*4882a593Smuzhiyun #include <asm/arch/davinci_misc.h>
28*4882a593Smuzhiyun #include <linux/errno.h>
29*4882a593Smuzhiyun #include <asm/gpio.h>
30*4882a593Smuzhiyun #include <hwconfig.h>
31*4882a593Smuzhiyun #include <bootstage.h>
32*4882a593Smuzhiyun #include <asm/mach-types.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
37*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
38*4882a593Smuzhiyun #define HAS_RMII 1
39*4882a593Smuzhiyun #else
40*4882a593Smuzhiyun #define HAS_RMII 0
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_TI_EMAC */
43*4882a593Smuzhiyun 
dsp_lpsc_on(unsigned domain,unsigned int id)44*4882a593Smuzhiyun void dsp_lpsc_on(unsigned domain, unsigned int id)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
47*4882a593Smuzhiyun 	struct davinci_psc_regs *psc_regs;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	psc_regs = davinci_psc0_regs;
50*4882a593Smuzhiyun 	mdstat = &psc_regs->psc0.mdstat[id];
51*4882a593Smuzhiyun 	mdctl = &psc_regs->psc0.mdctl[id];
52*4882a593Smuzhiyun 	ptstat = &psc_regs->ptstat;
53*4882a593Smuzhiyun 	ptcmd = &psc_regs->ptcmd;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	while (*ptstat & (0x1 << domain))
56*4882a593Smuzhiyun 		;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	if ((*mdstat & 0x1f) == 0x03)
59*4882a593Smuzhiyun 		return;                 /* Already on and enabled */
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	*mdctl |= 0x03;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	*ptcmd = 0x1 << domain;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	while (*ptstat & (0x1 << domain))
66*4882a593Smuzhiyun 		;
67*4882a593Smuzhiyun 	while ((*mdstat & 0x1f) != 0x03)
68*4882a593Smuzhiyun 		;		/* Probably an overkill... */
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
dspwake(void)71*4882a593Smuzhiyun static void dspwake(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
74*4882a593Smuzhiyun 	u32 val;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	/* if the device is ARM only, return */
77*4882a593Smuzhiyun 	if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
78*4882a593Smuzhiyun 		return;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
81*4882a593Smuzhiyun 		return;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	*resetvect++ = 0x1E000; /* DSP Idle */
84*4882a593Smuzhiyun 	/* clear out the next 10 words as NOP */
85*4882a593Smuzhiyun 	memset(resetvect, 0, sizeof(unsigned) * 10);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	/* setup the DSP reset vector */
88*4882a593Smuzhiyun 	writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
91*4882a593Smuzhiyun 	val = readl(PSC0_MDCTL + (15 * 4));
92*4882a593Smuzhiyun 	val |= 0x100;
93*4882a593Smuzhiyun 	writel(val, (PSC0_MDCTL + (15 * 4)));
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
misc_init_r(void)96*4882a593Smuzhiyun int misc_init_r(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	dspwake();
99*4882a593Smuzhiyun 	return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static const struct pinmux_config gpio_pins[] = {
103*4882a593Smuzhiyun 	/* GP7[14] selects bootmode*/
104*4882a593Smuzhiyun 	{ pinmux(16), 8, 3 },	/* GP7[14] */
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun const struct pinmux_resource pinmuxes[] = {
108*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
109*4882a593Smuzhiyun 	PINMUX_ITEM(emac_pins_mdio),
110*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
111*4882a593Smuzhiyun 	PINMUX_ITEM(emac_pins_rmii),
112*4882a593Smuzhiyun #else
113*4882a593Smuzhiyun 	PINMUX_ITEM(emac_pins_mii),
114*4882a593Smuzhiyun #endif
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun 	PINMUX_ITEM(uart2_pins_txrx),
117*4882a593Smuzhiyun 	PINMUX_ITEM(uart2_pins_rtscts),
118*4882a593Smuzhiyun 	PINMUX_ITEM(uart0_pins_txrx),
119*4882a593Smuzhiyun 	PINMUX_ITEM(uart0_pins_rtscts),
120*4882a593Smuzhiyun #ifdef CONFIG_NAND_DAVINCI
121*4882a593Smuzhiyun 	PINMUX_ITEM(emifa_pins_cs3),
122*4882a593Smuzhiyun 	PINMUX_ITEM(emifa_pins_nand),
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun 	PINMUX_ITEM(gpio_pins),
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun const struct lpsc_resource lpsc[] = {
130*4882a593Smuzhiyun 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
131*4882a593Smuzhiyun 	{ DAVINCI_LPSC_EMAC },	/* image download */
132*4882a593Smuzhiyun 	{ DAVINCI_LPSC_UART2 },	/* console */
133*4882a593Smuzhiyun 	{ DAVINCI_LPSC_UART0 },	/* console */
134*4882a593Smuzhiyun 	{ DAVINCI_LPSC_GPIO },
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun const int lpsc_size = ARRAY_SIZE(lpsc);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
140*4882a593Smuzhiyun #define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
141*4882a593Smuzhiyun #endif
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define REV_AM18X_EVM		0x100
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /*
146*4882a593Smuzhiyun  * get_board_rev() - setup to pass kernel board revision information
147*4882a593Smuzhiyun  * Returns:
148*4882a593Smuzhiyun  * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
149*4882a593Smuzhiyun  *		0000b - 300 MHz
150*4882a593Smuzhiyun  *		0001b - 372 MHz
151*4882a593Smuzhiyun  *		0010b - 408 MHz
152*4882a593Smuzhiyun  *		0011b - 456 MHz
153*4882a593Smuzhiyun  */
get_board_rev(void)154*4882a593Smuzhiyun u32 get_board_rev(void)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	char *s;
157*4882a593Smuzhiyun 	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
158*4882a593Smuzhiyun 	u32 rev = 0;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	s = env_get("maxcpuclk");
161*4882a593Smuzhiyun 	if (s)
162*4882a593Smuzhiyun 		maxcpuclk = simple_strtoul(s, NULL, 10);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	if (maxcpuclk >= 456000000)
165*4882a593Smuzhiyun 		rev = 3;
166*4882a593Smuzhiyun 	else if (maxcpuclk >= 408000000)
167*4882a593Smuzhiyun 		rev = 2;
168*4882a593Smuzhiyun 	else if (maxcpuclk >= 372000000)
169*4882a593Smuzhiyun 		rev = 1;
170*4882a593Smuzhiyun #ifdef CONFIG_DA850_AM18X_EVM
171*4882a593Smuzhiyun 	rev |= REV_AM18X_EVM;
172*4882a593Smuzhiyun #endif
173*4882a593Smuzhiyun 	return rev;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
board_early_init_f(void)176*4882a593Smuzhiyun int board_early_init_f(void)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	/*
179*4882a593Smuzhiyun 	 * Power on required peripherals
180*4882a593Smuzhiyun 	 * ARM does not have access by default to PSC0 and PSC1
181*4882a593Smuzhiyun 	 * assuming here that the DSP bootloader has set the IOPU
182*4882a593Smuzhiyun 	 * such that PSC access is available to ARM
183*4882a593Smuzhiyun 	 */
184*4882a593Smuzhiyun 	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
185*4882a593Smuzhiyun 		return 1;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
board_init(void)190*4882a593Smuzhiyun int board_init(void)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun 	irq_init();
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	/* arch number of the board */
195*4882a593Smuzhiyun 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	/* address of boot parameters */
198*4882a593Smuzhiyun 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* setup the SUSPSRC for ARM to control emulation suspend */
201*4882a593Smuzhiyun 	writel(readl(&davinci_syscfg_regs->suspsrc) &
202*4882a593Smuzhiyun 	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
203*4882a593Smuzhiyun 		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
204*4882a593Smuzhiyun 		 DAVINCI_SYSCFG_SUSPSRC_UART0),
205*4882a593Smuzhiyun 	       &davinci_syscfg_regs->suspsrc);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* configure pinmux settings */
208*4882a593Smuzhiyun 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
209*4882a593Smuzhiyun 		return 1;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
212*4882a593Smuzhiyun 	davinci_emac_mii_mode_sel(HAS_RMII);
213*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_TI_EMAC */
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	/* enable the console UART */
216*4882a593Smuzhiyun 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
217*4882a593Smuzhiyun 		DAVINCI_UART_PWREMU_MGMT_UTRST),
218*4882a593Smuzhiyun #if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
219*4882a593Smuzhiyun 	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
220*4882a593Smuzhiyun #else
221*4882a593Smuzhiyun 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
222*4882a593Smuzhiyun #endif
223*4882a593Smuzhiyun 	return 0;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun  * Initializes on-board ethernet controllers.
229*4882a593Smuzhiyun  */
board_eth_init(bd_t * bis)230*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	if (!davinci_emac_initialize()) {
233*4882a593Smuzhiyun 		printf("Error: Ethernet init failed!\n");
234*4882a593Smuzhiyun 		return -1;
235*4882a593Smuzhiyun 	}
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	return 0;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_TI_EMAC */
240*4882a593Smuzhiyun 
init_led(int gpio,char * name,int val)241*4882a593Smuzhiyun static int init_led(int gpio, char *name, int val)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	int ret;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	ret = gpio_request(gpio, name);
246*4882a593Smuzhiyun 	if (ret)
247*4882a593Smuzhiyun 		return -1;
248*4882a593Smuzhiyun 	ret = gpio_direction_output(gpio, val);
249*4882a593Smuzhiyun 	if (ret)
250*4882a593Smuzhiyun 		return -1;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	return gpio;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun #define LED_ON	0
256*4882a593Smuzhiyun #define LED_OFF	1
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun #if !defined(CONFIG_SPL_BUILD)
259*4882a593Smuzhiyun #ifdef CONFIG_SHOW_BOOT_PROGRESS
show_boot_progress(int status)260*4882a593Smuzhiyun void show_boot_progress(int status)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	static int red;
263*4882a593Smuzhiyun 	static int green;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (red == 0)
266*4882a593Smuzhiyun 		red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
267*4882a593Smuzhiyun 	if (red != CONFIG_IPAM390_GPIO_LED_RED)
268*4882a593Smuzhiyun 		return;
269*4882a593Smuzhiyun 	if (green == 0)
270*4882a593Smuzhiyun 		green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green",
271*4882a593Smuzhiyun 				 LED_OFF);
272*4882a593Smuzhiyun 	if (green != CONFIG_IPAM390_GPIO_LED_GREEN)
273*4882a593Smuzhiyun 		return;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	switch (status) {
276*4882a593Smuzhiyun 	case BOOTSTAGE_ID_RUN_OS:
277*4882a593Smuzhiyun 		/*
278*4882a593Smuzhiyun 		 * set normal state
279*4882a593Smuzhiyun 		 * LED Red  : on
280*4882a593Smuzhiyun 		 * LED green: off
281*4882a593Smuzhiyun 		 */
282*4882a593Smuzhiyun 		gpio_set_value(red, LED_ON);
283*4882a593Smuzhiyun 		gpio_set_value(green, LED_OFF);
284*4882a593Smuzhiyun 		break;
285*4882a593Smuzhiyun 	case BOOTSTAGE_ID_MAIN_LOOP:
286*4882a593Smuzhiyun 		/*
287*4882a593Smuzhiyun 		 * U-Boot operation
288*4882a593Smuzhiyun 		 * LED Red  : on
289*4882a593Smuzhiyun 		 * LED green: on
290*4882a593Smuzhiyun 		 */
291*4882a593Smuzhiyun 		gpio_set_value(red, LED_ON);
292*4882a593Smuzhiyun 		gpio_set_value(green, LED_ON);
293*4882a593Smuzhiyun 		break;
294*4882a593Smuzhiyun 	}
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun #endif
297*4882a593Smuzhiyun #endif
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)300*4882a593Smuzhiyun int spl_start_uboot(void)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun 	int ret;
303*4882a593Smuzhiyun 	int bootmode = 0;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	/*
306*4882a593Smuzhiyun 	 * GP7[14] selects bootmode:
307*4882a593Smuzhiyun 	 * 1: boot linux
308*4882a593Smuzhiyun 	 * 0: boot u-boot
309*4882a593Smuzhiyun 	 * if error accessing gpio boot U-Boot
310*4882a593Smuzhiyun 	 *
311*4882a593Smuzhiyun 	 * SPL bootmode
312*4882a593Smuzhiyun 	 * 0: boot linux
313*4882a593Smuzhiyun 	 * 1: boot u-boot
314*4882a593Smuzhiyun 	 */
315*4882a593Smuzhiyun 	ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode");
316*4882a593Smuzhiyun 	if (ret)
317*4882a593Smuzhiyun 		bootmode = 1;
318*4882a593Smuzhiyun 	if (!bootmode) {
319*4882a593Smuzhiyun 		ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE);
320*4882a593Smuzhiyun 		if (ret)
321*4882a593Smuzhiyun 			bootmode = 1;
322*4882a593Smuzhiyun 	}
323*4882a593Smuzhiyun 	if (!bootmode)
324*4882a593Smuzhiyun 		ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE);
325*4882a593Smuzhiyun 	if (!bootmode)
326*4882a593Smuzhiyun 		if (ret == 0)
327*4882a593Smuzhiyun 			bootmode = 1;
328*4882a593Smuzhiyun 	/*
329*4882a593Smuzhiyun 	 * LED red  : on
330*4882a593Smuzhiyun 	 * LED green: off
331*4882a593Smuzhiyun 	 */
332*4882a593Smuzhiyun 	init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
333*4882a593Smuzhiyun 	init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
334*4882a593Smuzhiyun 	return bootmode;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun #endif
337