1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013-2015 Arcturus Networks, Inc.
3*4882a593Smuzhiyun * http://www.arcturusnetworks.com/products/ucp1020/
4*4882a593Smuzhiyun * by Oleksandr G Zhadan et al.
5*4882a593Smuzhiyun * based on board/freescale/p1_p2_rdb_pc/spl.c
6*4882a593Smuzhiyun * original copyright follows:
7*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <command.h>
14*4882a593Smuzhiyun #include <hwconfig.h>
15*4882a593Smuzhiyun #include <pci.h>
16*4882a593Smuzhiyun #include <i2c.h>
17*4882a593Smuzhiyun #include <miiphy.h>
18*4882a593Smuzhiyun #include <linux/libfdt.h>
19*4882a593Smuzhiyun #include <fdt_support.h>
20*4882a593Smuzhiyun #include <fsl_mdio.h>
21*4882a593Smuzhiyun #include <tsec.h>
22*4882a593Smuzhiyun #include <ioports.h>
23*4882a593Smuzhiyun #include <netdev.h>
24*4882a593Smuzhiyun #include <micrel.h>
25*4882a593Smuzhiyun #include <spi_flash.h>
26*4882a593Smuzhiyun #include <mmc.h>
27*4882a593Smuzhiyun #include <linux/ctype.h>
28*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
29*4882a593Smuzhiyun #include <asm/gpio.h>
30*4882a593Smuzhiyun #include <asm/processor.h>
31*4882a593Smuzhiyun #include <asm/mmu.h>
32*4882a593Smuzhiyun #include <asm/cache.h>
33*4882a593Smuzhiyun #include <asm/immap_85xx.h>
34*4882a593Smuzhiyun #include <asm/fsl_pci.h>
35*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
36*4882a593Smuzhiyun #include <asm/io.h>
37*4882a593Smuzhiyun #include <asm/fsl_law.h>
38*4882a593Smuzhiyun #include <asm/fsl_lbc.h>
39*4882a593Smuzhiyun #include <asm/mp.h>
40*4882a593Smuzhiyun #include "ucp1020.h"
41*4882a593Smuzhiyun
spi_set_speed(struct spi_slave * slave,uint hz)42*4882a593Smuzhiyun void spi_set_speed(struct spi_slave *slave, uint hz)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun /* TO DO: It's actially have to be in spi/ */
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * To be compatible with cmd_gpio
49*4882a593Smuzhiyun */
name_to_gpio(const char * name)50*4882a593Smuzhiyun int name_to_gpio(const char *name)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int gpio = 31 - simple_strtoul(name, NULL, 10);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (gpio < 16)
55*4882a593Smuzhiyun gpio = -1;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return gpio;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
board_gpio_init(void)60*4882a593Smuzhiyun void board_gpio_init(void)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun int i;
63*4882a593Smuzhiyun char envname[8], *val;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun for (i = 0; i < GPIO_MAX_NUM; i++) {
66*4882a593Smuzhiyun sprintf(envname, "GPIO%d", i);
67*4882a593Smuzhiyun val = env_get(envname);
68*4882a593Smuzhiyun if (val) {
69*4882a593Smuzhiyun char direction = toupper(val[0]);
70*4882a593Smuzhiyun char level = toupper(val[1]);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (direction == 'I') {
73*4882a593Smuzhiyun gpio_direction_input(i);
74*4882a593Smuzhiyun } else {
75*4882a593Smuzhiyun if (direction == 'O') {
76*4882a593Smuzhiyun if (level == '1')
77*4882a593Smuzhiyun gpio_direction_output(i, 1);
78*4882a593Smuzhiyun else
79*4882a593Smuzhiyun gpio_direction_output(i, 0);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun val = env_get("PCIE_OFF");
86*4882a593Smuzhiyun if (val) {
87*4882a593Smuzhiyun gpio_direction_input(GPIO_PCIE1_EN);
88*4882a593Smuzhiyun gpio_direction_input(GPIO_PCIE2_EN);
89*4882a593Smuzhiyun } else {
90*4882a593Smuzhiyun gpio_direction_output(GPIO_PCIE1_EN, 1);
91*4882a593Smuzhiyun gpio_direction_output(GPIO_PCIE2_EN, 1);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun val = env_get("SDHC_CDWP_OFF");
95*4882a593Smuzhiyun if (!val) {
96*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun setbits_be32(&gur->pmuxcr,
99*4882a593Smuzhiyun (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
board_early_init_f(void)103*4882a593Smuzhiyun int board_early_init_f(void)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun return 0; /* Just in case. Could be disable in config file */
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
checkboard(void)108*4882a593Smuzhiyun int checkboard(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
111*4882a593Smuzhiyun board_gpio_init();
112*4882a593Smuzhiyun printf("SD/MMC: 4-bit Mode\n");
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #ifdef CONFIG_PCI
pci_init_board(void)118*4882a593Smuzhiyun void pci_init_board(void)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun fsl_pcie_init_board(0);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun #endif
123*4882a593Smuzhiyun
board_early_init_r(void)124*4882a593Smuzhiyun int board_early_init_r(void)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
127*4882a593Smuzhiyun const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * Remap Boot flash region to caching-inhibited
131*4882a593Smuzhiyun * so that flash can be erased properly.
132*4882a593Smuzhiyun */
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* Flush d-cache and invalidate i-cache of any FLASH data */
135*4882a593Smuzhiyun flush_dcache();
136*4882a593Smuzhiyun invalidate_icache();
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* invalidate existing TLB entry for flash */
139*4882a593Smuzhiyun disable_tlb(flash_esel);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
142*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
143*4882a593Smuzhiyun 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
board_phy_config(struct phy_device * phydev)148*4882a593Smuzhiyun int board_phy_config(struct phy_device *phydev)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun #if defined(CONFIG_PHY_MICREL_KSZ9021)
151*4882a593Smuzhiyun int regval;
152*4882a593Smuzhiyun static int cnt;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (cnt++ == 0)
155*4882a593Smuzhiyun printf("PHYs address [");
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
158*4882a593Smuzhiyun regval =
159*4882a593Smuzhiyun ksz9021_phy_extended_read(phydev,
160*4882a593Smuzhiyun MII_KSZ9021_EXT_STRAP_STATUS);
161*4882a593Smuzhiyun /*
162*4882a593Smuzhiyun * min rx data delay
163*4882a593Smuzhiyun */
164*4882a593Smuzhiyun ksz9021_phy_extended_write(phydev,
165*4882a593Smuzhiyun MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
166*4882a593Smuzhiyun 0x6666);
167*4882a593Smuzhiyun /*
168*4882a593Smuzhiyun * max rx/tx clock delay, min rx/tx control
169*4882a593Smuzhiyun */
170*4882a593Smuzhiyun ksz9021_phy_extended_write(phydev,
171*4882a593Smuzhiyun MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
172*4882a593Smuzhiyun 0xf6f6);
173*4882a593Smuzhiyun printf("0x%x", (regval & 0x1f));
174*4882a593Smuzhiyun } else {
175*4882a593Smuzhiyun printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun if (cnt == 3)
178*4882a593Smuzhiyun printf("] ");
179*4882a593Smuzhiyun else
180*4882a593Smuzhiyun printf(",");
181*4882a593Smuzhiyun #endif
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
184*4882a593Smuzhiyun regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
185*4882a593Smuzhiyun if (regval >= 0)
186*4882a593Smuzhiyun printf(" (ADDR 0x%x) ", regval & 0x1f);
187*4882a593Smuzhiyun #endif
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
last_stage_init(void)192*4882a593Smuzhiyun int last_stage_init(void)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun static char newkernelargs[256];
195*4882a593Smuzhiyun static u8 id1[16];
196*4882a593Smuzhiyun static u8 id2;
197*4882a593Smuzhiyun struct mmc *mmc;
198*4882a593Smuzhiyun char *sval, *kval;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
201*4882a593Smuzhiyun printf("Error reading i2c IDT6V49205B information!\n");
202*4882a593Smuzhiyun } else {
203*4882a593Smuzhiyun printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
204*4882a593Smuzhiyun i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
205*4882a593Smuzhiyun if (!(id1[1] & 0x02)) {
206*4882a593Smuzhiyun id1[1] |= 0x02;
207*4882a593Smuzhiyun i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
208*4882a593Smuzhiyun asm("nop; nop");
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
213*4882a593Smuzhiyun printf("Error reading i2c NCT72 information!\n");
214*4882a593Smuzhiyun else
215*4882a593Smuzhiyun printf("NCT72(0x%x): ready\n", id2);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun kval = env_get("kernelargs");
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun mmc = find_mmc_device(0);
220*4882a593Smuzhiyun if (mmc)
221*4882a593Smuzhiyun if (!mmc_init(mmc)) {
222*4882a593Smuzhiyun printf("MMC/SD card detected\n");
223*4882a593Smuzhiyun if (kval) {
224*4882a593Smuzhiyun int n = strlen(defkargs);
225*4882a593Smuzhiyun char *tmp = strstr(kval, defkargs);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun *tmp = 0;
228*4882a593Smuzhiyun strcpy(newkernelargs, kval);
229*4882a593Smuzhiyun strcat(newkernelargs, " ");
230*4882a593Smuzhiyun strcat(newkernelargs, mmckargs);
231*4882a593Smuzhiyun strcat(newkernelargs, " ");
232*4882a593Smuzhiyun strcat(newkernelargs, &tmp[n]);
233*4882a593Smuzhiyun env_set("kernelargs", newkernelargs);
234*4882a593Smuzhiyun } else {
235*4882a593Smuzhiyun env_set("kernelargs", mmckargs);
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun get_arc_info();
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (kval) {
241*4882a593Smuzhiyun sval = env_get("SERIAL");
242*4882a593Smuzhiyun if (sval) {
243*4882a593Smuzhiyun strcpy(newkernelargs, "SN=");
244*4882a593Smuzhiyun strcat(newkernelargs, sval);
245*4882a593Smuzhiyun strcat(newkernelargs, " ");
246*4882a593Smuzhiyun strcat(newkernelargs, kval);
247*4882a593Smuzhiyun env_set("kernelargs", newkernelargs);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun } else {
250*4882a593Smuzhiyun printf("Error reading kernelargs env variable!\n");
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun return 0;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
board_eth_init(bd_t * bis)256*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun struct fsl_pq_mdio_info mdio_info;
259*4882a593Smuzhiyun struct tsec_info_struct tsec_info[4];
260*4882a593Smuzhiyun #ifdef CONFIG_TSEC2
261*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
262*4882a593Smuzhiyun #endif
263*4882a593Smuzhiyun int num = 0;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun #ifdef CONFIG_TSEC1
266*4882a593Smuzhiyun SET_STD_TSEC_INFO(tsec_info[num], 1);
267*4882a593Smuzhiyun num++;
268*4882a593Smuzhiyun #endif
269*4882a593Smuzhiyun #ifdef CONFIG_TSEC2
270*4882a593Smuzhiyun SET_STD_TSEC_INFO(tsec_info[num], 2);
271*4882a593Smuzhiyun if (is_serdes_configured(SGMII_TSEC2)) {
272*4882a593Smuzhiyun if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
273*4882a593Smuzhiyun puts("eTSEC2 is in sgmii mode.\n");
274*4882a593Smuzhiyun tsec_info[num].flags |= TSEC_SGMII;
275*4882a593Smuzhiyun tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun num++;
279*4882a593Smuzhiyun #endif
280*4882a593Smuzhiyun #ifdef CONFIG_TSEC3
281*4882a593Smuzhiyun SET_STD_TSEC_INFO(tsec_info[num], 3);
282*4882a593Smuzhiyun num++;
283*4882a593Smuzhiyun #endif
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (!num) {
286*4882a593Smuzhiyun printf("No TSECs initialized\n");
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
291*4882a593Smuzhiyun mdio_info.name = DEFAULT_MII_NAME;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun fsl_pq_mdio_init(bis, &mdio_info);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun tsec_eth_init(bis, tsec_info, num);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun return pci_eth_init(bis);
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)301*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun phys_addr_t base;
304*4882a593Smuzhiyun phys_size_t size;
305*4882a593Smuzhiyun const char *soc_usb_compat = "fsl-usb2-dr";
306*4882a593Smuzhiyun int err, usb1_off, usb2_off;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun ft_cpu_setup(blob, bd);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun base = env_get_bootm_low();
311*4882a593Smuzhiyun size = env_get_bootm_size();
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun fdt_fixup_memory(blob, (u64)base, (u64)size);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun FT_FSL_PCI_SETUP;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun #if defined(CONFIG_HAS_FSL_DR_USB)
318*4882a593Smuzhiyun fsl_fdt_fixup_dr_usb(blob, bd);
319*4882a593Smuzhiyun #endif
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
322*4882a593Smuzhiyun /* Delete eLBC node as it is muxed with USB2 controller */
323*4882a593Smuzhiyun if (hwconfig("usb2")) {
324*4882a593Smuzhiyun const char *soc_elbc_compat = "fsl,p1020-elbc";
325*4882a593Smuzhiyun int off = fdt_node_offset_by_compatible(blob, -1,
326*4882a593Smuzhiyun soc_elbc_compat);
327*4882a593Smuzhiyun if (off < 0) {
328*4882a593Smuzhiyun printf
329*4882a593Smuzhiyun ("WARNING: could not find compatible node %s: %s\n",
330*4882a593Smuzhiyun soc_elbc_compat, fdt_strerror(off));
331*4882a593Smuzhiyun return off;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun err = fdt_del_node(blob, off);
334*4882a593Smuzhiyun if (err < 0) {
335*4882a593Smuzhiyun printf("WARNING: could not remove %s: %s\n",
336*4882a593Smuzhiyun soc_elbc_compat, fdt_strerror(err));
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun return err;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun #endif
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /* Delete USB2 node as it is muxed with eLBC */
343*4882a593Smuzhiyun usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
344*4882a593Smuzhiyun if (usb1_off < 0) {
345*4882a593Smuzhiyun printf("WARNING: could not find compatible node %s: %s.\n",
346*4882a593Smuzhiyun soc_usb_compat, fdt_strerror(usb1_off));
347*4882a593Smuzhiyun return usb1_off;
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun usb2_off =
350*4882a593Smuzhiyun fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
351*4882a593Smuzhiyun if (usb2_off < 0) {
352*4882a593Smuzhiyun printf("WARNING: could not find compatible node %s: %s.\n",
353*4882a593Smuzhiyun soc_usb_compat, fdt_strerror(usb2_off));
354*4882a593Smuzhiyun return usb2_off;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun err = fdt_del_node(blob, usb2_off);
357*4882a593Smuzhiyun if (err < 0) {
358*4882a593Smuzhiyun printf("WARNING: could not remove %s: %s.\n",
359*4882a593Smuzhiyun soc_usb_compat, fdt_strerror(err));
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun return 0;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun #endif
364