1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013-2015 Arcturus Networks, Inc 3*4882a593Smuzhiyun * http://www.arcturusnetworks.com/products/ucp1020/ 4*4882a593Smuzhiyun * based on board/freescale/p1_p2_rdb_pc/tlb.c 5*4882a593Smuzhiyun * original copyright follows: 6*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/mmu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 15*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 16*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 17*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 18*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, 0, 19*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 20*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 21*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 22*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 25*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 26*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, 0, 27*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 28*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 29*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 30*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, 0, 31*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* TLB 1 */ 34*4882a593Smuzhiyun /* *I*** - Covers boot page */ 35*4882a593Smuzhiyun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 36*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, 37*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 1), 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* *I*G* - CCSRBAR */ 40*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 41*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 42*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1M, 1), 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 45*4882a593Smuzhiyun /* W**G* - Flash/promjet, localbus */ 46*4882a593Smuzhiyun /* This will be changed to *I*G* after relocation to RAM. */ 47*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 48*4882a593Smuzhiyun MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, 49*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_64M, 1), 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #ifdef CONFIG_PCI 52*4882a593Smuzhiyun /* *I*G* - PCI memory 1.5G */ 53*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 54*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 55*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_1G, 1), 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* *I*G* - PCI I/O effective: 192K */ 58*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 59*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 60*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_256K, 1), 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifdef CONFIG_VSC7385_ENET 64*4882a593Smuzhiyun /* *I*G - VSC7385 Switch */ 65*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, 66*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 67*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_1M, 1), 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun #endif /* not SPL */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_BASE 72*4882a593Smuzhiyun /* *I*G - NAND */ 73*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 74*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 75*4882a593Smuzhiyun 0, 7, BOOKE_PAGESZ_1M, 1), 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #if defined(CONFIG_SYS_RAMBOOT) || \ 79*4882a593Smuzhiyun (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 80*4882a593Smuzhiyun /* *I*G - eSDHC/eSPI/NAND boot */ 81*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 82*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, 0, 83*4882a593Smuzhiyun 0, 8, BOOKE_PAGESZ_1G, 1), 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* RAMBOOT/SPL */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #ifdef CONFIG_SYS_INIT_L2_ADDR 88*4882a593Smuzhiyun /* *I*G - L2SRAM */ 89*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 90*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, 91*4882a593Smuzhiyun 0, 11, BOOKE_PAGESZ_256K, 1), 92*4882a593Smuzhiyun #if CONFIG_SYS_L2_SIZE >= (256 << 10) 93*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 94*4882a593Smuzhiyun CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 95*4882a593Smuzhiyun MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 96*4882a593Smuzhiyun 0, 12, BOOKE_PAGESZ_256K, 1) 97*4882a593Smuzhiyun #endif 98*4882a593Smuzhiyun #endif 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 102