1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013-2015 Arcturus Networks, Inc.
3*4882a593Smuzhiyun * http://www.arcturusnetworks.com/products/ucp1020/
4*4882a593Smuzhiyun * based on board/freescale/p1_p2_rdb_pc/spl.c
5*4882a593Smuzhiyun * original copyright follows:
6*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <console.h>
13*4882a593Smuzhiyun #include <environment.h>
14*4882a593Smuzhiyun #include <ns16550.h>
15*4882a593Smuzhiyun #include <malloc.h>
16*4882a593Smuzhiyun #include <mmc.h>
17*4882a593Smuzhiyun #include <nand.h>
18*4882a593Smuzhiyun #include <i2c.h>
19*4882a593Smuzhiyun #include <fsl_esdhc.h>
20*4882a593Smuzhiyun #include <spi_flash.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static const u32 sysclk_tbl[] = {
25*4882a593Smuzhiyun 66666000, 7499900, 83332500, 8999900,
26*4882a593Smuzhiyun 99999000, 11111000, 12499800, 13333200
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
get_effective_memsize(void)29*4882a593Smuzhiyun phys_size_t get_effective_memsize(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun return CONFIG_SYS_L2_SIZE;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
board_init_f(ulong bootflag)34*4882a593Smuzhiyun void board_init_f(ulong bootflag)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun u32 plat_ratio, bus_clk;
37*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun console_init_f();
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Set pmuxcr to allow both i2c1 and i2c2 */
42*4882a593Smuzhiyun setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
43*4882a593Smuzhiyun setbits_be32(&gur->pmuxcr,
44*4882a593Smuzhiyun in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Read back the register to synchronize the write. */
47*4882a593Smuzhiyun in_be32(&gur->pmuxcr);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #ifdef CONFIG_SPL_SPI_BOOT
50*4882a593Smuzhiyun clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
51*4882a593Smuzhiyun #endif
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* initialize selected port with appropriate baud rate */
54*4882a593Smuzhiyun plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
55*4882a593Smuzhiyun plat_ratio >>= 1;
56*4882a593Smuzhiyun bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
57*4882a593Smuzhiyun gd->bus_clk = bus_clk;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
60*4882a593Smuzhiyun bus_clk / 16 / CONFIG_BAUDRATE);
61*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
62*4882a593Smuzhiyun puts("\nSD boot...\n");
63*4882a593Smuzhiyun #elif defined(CONFIG_SPL_SPI_BOOT)
64*4882a593Smuzhiyun puts("\nSPI Flash boot...\n");
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* copy code to RAM and jump to it - this should not return */
68*4882a593Smuzhiyun /* NOTE - code has to be copied out of NAND buffer before
69*4882a593Smuzhiyun * other blocks can be read.
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
board_init_r(gd_t * gd,ulong dest_addr)74*4882a593Smuzhiyun void board_init_r(gd_t *gd, ulong dest_addr)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun /* Pointer is writable since we allocated a register for it */
77*4882a593Smuzhiyun gd = (gd_t *)CONFIG_SPL_GD_ADDR;
78*4882a593Smuzhiyun bd_t *bd;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun memset(gd, 0, sizeof(gd_t));
81*4882a593Smuzhiyun bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
82*4882a593Smuzhiyun memset(bd, 0, sizeof(bd_t));
83*4882a593Smuzhiyun gd->bd = bd;
84*4882a593Smuzhiyun bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
85*4882a593Smuzhiyun bd->bi_memsize = CONFIG_SYS_L2_SIZE;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun arch_cpu_init();
88*4882a593Smuzhiyun get_clocks();
89*4882a593Smuzhiyun mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
90*4882a593Smuzhiyun CONFIG_SPL_RELOC_MALLOC_SIZE);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #ifndef CONFIG_SPL_NAND_BOOT
93*4882a593Smuzhiyun env_init();
94*4882a593Smuzhiyun #endif
95*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
96*4882a593Smuzhiyun mmc_initialize(bd);
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun /* relocate environment function pointers etc. */
99*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
100*4882a593Smuzhiyun nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
101*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
102*4882a593Smuzhiyun gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
103*4882a593Smuzhiyun gd->env_valid = ENV_VALID;
104*4882a593Smuzhiyun #else
105*4882a593Smuzhiyun env_relocate();
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C
109*4882a593Smuzhiyun i2c_init_all();
110*4882a593Smuzhiyun #else
111*4882a593Smuzhiyun i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
112*4882a593Smuzhiyun #endif
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun dram_init();
115*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
116*4882a593Smuzhiyun puts("Tertiary program loader running in sram...");
117*4882a593Smuzhiyun #else
118*4882a593Smuzhiyun puts("Second program loader running in sram...\n");
119*4882a593Smuzhiyun #endif
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_BOOT
122*4882a593Smuzhiyun mmc_boot();
123*4882a593Smuzhiyun #elif defined(CONFIG_SPL_NAND_BOOT)
124*4882a593Smuzhiyun nand_boot();
125*4882a593Smuzhiyun #endif
126*4882a593Smuzhiyun }
127