1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _XTENSA_REGS_H 8*4882a593Smuzhiyun #define _XTENSA_REGS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Special registers */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define IBREAKA 128 13*4882a593Smuzhiyun #define DBREAKA 144 14*4882a593Smuzhiyun #define DBREAKC 160 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Special names for read-only and write-only interrupt registers */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define INTREAD 226 19*4882a593Smuzhiyun #define INTSET 226 20*4882a593Smuzhiyun #define INTCLEAR 227 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* EXCCAUSE register fields */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define EXCCAUSE_EXCCAUSE_SHIFT 0 25*4882a593Smuzhiyun #define EXCCAUSE_EXCCAUSE_MASK 0x3F 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define EXCCAUSE_ILLEGAL_INSTRUCTION 0 28*4882a593Smuzhiyun #define EXCCAUSE_SYSTEM_CALL 1 29*4882a593Smuzhiyun #define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 30*4882a593Smuzhiyun #define EXCCAUSE_LOAD_STORE_ERROR 3 31*4882a593Smuzhiyun #define EXCCAUSE_LEVEL1_INTERRUPT 4 32*4882a593Smuzhiyun #define EXCCAUSE_ALLOCA 5 33*4882a593Smuzhiyun #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 34*4882a593Smuzhiyun #define EXCCAUSE_SPECULATION 7 35*4882a593Smuzhiyun #define EXCCAUSE_PRIVILEGED 8 36*4882a593Smuzhiyun #define EXCCAUSE_UNALIGNED 9 37*4882a593Smuzhiyun #define EXCCAUSE_INSTR_DATA_ERROR 12 38*4882a593Smuzhiyun #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 39*4882a593Smuzhiyun #define EXCCAUSE_INSTR_ADDR_ERROR 14 40*4882a593Smuzhiyun #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 41*4882a593Smuzhiyun #define EXCCAUSE_ITLB_MISS 16 42*4882a593Smuzhiyun #define EXCCAUSE_ITLB_MULTIHIT 17 43*4882a593Smuzhiyun #define EXCCAUSE_ITLB_PRIVILEGE 18 44*4882a593Smuzhiyun #define EXCCAUSE_ITLB_SIZE_RESTRICTION 19 45*4882a593Smuzhiyun #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 46*4882a593Smuzhiyun #define EXCCAUSE_DTLB_MISS 24 47*4882a593Smuzhiyun #define EXCCAUSE_DTLB_MULTIHIT 25 48*4882a593Smuzhiyun #define EXCCAUSE_DTLB_PRIVILEGE 26 49*4882a593Smuzhiyun #define EXCCAUSE_DTLB_SIZE_RESTRICTION 27 50*4882a593Smuzhiyun #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 51*4882a593Smuzhiyun #define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 52*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR0_DISABLED 32 53*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR1_DISABLED 33 54*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR2_DISABLED 34 55*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR3_DISABLED 35 56*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR4_DISABLED 36 57*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR5_DISABLED 37 58*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR6_DISABLED 38 59*4882a593Smuzhiyun #define EXCCAUSE_COPROCESSOR7_DISABLED 39 60*4882a593Smuzhiyun #define EXCCAUSE_LAST 63 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* PS register fields */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PS_WOE_BIT 18 65*4882a593Smuzhiyun #define PS_CALLINC_SHIFT 16 66*4882a593Smuzhiyun #define PS_CALLINC_MASK 0x00030000 67*4882a593Smuzhiyun #define PS_OWB_SHIFT 8 68*4882a593Smuzhiyun #define PS_OWB_MASK 0x00000F00 69*4882a593Smuzhiyun #define PS_RING_SHIFT 6 70*4882a593Smuzhiyun #define PS_RING_MASK 0x000000C0 71*4882a593Smuzhiyun #define PS_UM_BIT 5 72*4882a593Smuzhiyun #define PS_EXCM_BIT 4 73*4882a593Smuzhiyun #define PS_INTLEVEL_SHIFT 0 74*4882a593Smuzhiyun #define PS_INTLEVEL_MASK 0x0000000F 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* DBREAKCn register fields */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define DBREAKC_MASK_BIT 0 79*4882a593Smuzhiyun #define DBREAKC_MASK_MASK 0x0000003F 80*4882a593Smuzhiyun #define DBREAKC_LOAD_BIT 30 81*4882a593Smuzhiyun #define DBREAKC_LOAD_MASK 0x40000000 82*4882a593Smuzhiyun #define DBREAKC_STOR_BIT 31 83*4882a593Smuzhiyun #define DBREAKC_STOR_MASK 0x80000000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* DEBUGCAUSE register fields */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */ 88*4882a593Smuzhiyun #define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */ 89*4882a593Smuzhiyun #define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */ 90*4882a593Smuzhiyun #define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */ 91*4882a593Smuzhiyun #define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */ 92*4882a593Smuzhiyun #define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif /* _XTENSA_SPECREG_H */ 95*4882a593Smuzhiyun 96