1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2006 Tensilica Inc. 3*4882a593Smuzhiyun * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _XTENSA_CACHEASM_H 9*4882a593Smuzhiyun #define _XTENSA_CACHEASM_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/cache.h> 12*4882a593Smuzhiyun #include <asm/asmmacro.h> 13*4882a593Smuzhiyun #include <linux/stringify.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PAGE_SIZE 4096 16*4882a593Smuzhiyun #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) 17*4882a593Smuzhiyun #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) 18*4882a593Smuzhiyun #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) 19*4882a593Smuzhiyun #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Define cache functions as macros here so that they can be used 23*4882a593Smuzhiyun * by the kernel and boot loader. We should consider moving them to a 24*4882a593Smuzhiyun * library that can be linked by both. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * Locking 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * ___unlock_dcache_all 29*4882a593Smuzhiyun * ___unlock_icache_all 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * Flush and invaldating 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * ___flush_invalidate_dcache_{all|range|page} 34*4882a593Smuzhiyun * ___flush_dcache_{all|range|page} 35*4882a593Smuzhiyun * ___invalidate_dcache_{all|range|page} 36*4882a593Smuzhiyun * ___invalidate_icache_{all|range|page} 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun .macro __loop_cache_all ar at insn size line_width 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun movi \ar, 0 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun __loopi \ar, \at, \size, (4 << (\line_width)) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun \insn \ar, 0 << (\line_width) 47*4882a593Smuzhiyun \insn \ar, 1 << (\line_width) 48*4882a593Smuzhiyun \insn \ar, 2 << (\line_width) 49*4882a593Smuzhiyun \insn \ar, 3 << (\line_width) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun __endla \ar, \at, 4 << (\line_width) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun .endm 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun .macro __loop_cache_range ar as at insn line_width 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun extui \at, \ar, 0, \line_width 59*4882a593Smuzhiyun add \as, \as, \at 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun __loops \ar, \as, \at, \line_width 62*4882a593Smuzhiyun \insn \ar, 0 63*4882a593Smuzhiyun __endla \ar, \at, (1 << (\line_width)) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun .endm 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun .macro __loop_cache_page ar at insn line_width 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun \insn \ar, 0 << (\line_width) 73*4882a593Smuzhiyun \insn \ar, 1 << (\line_width) 74*4882a593Smuzhiyun \insn \ar, 2 << (\line_width) 75*4882a593Smuzhiyun \insn \ar, 3 << (\line_width) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun __endla \ar, \at, 4 << (\line_width) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun .endm 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun .macro ___unlock_dcache_all ar at 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE 85*4882a593Smuzhiyun __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 86*4882a593Smuzhiyun #endif 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun .endm 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun .macro ___unlock_icache_all ar at 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE 94*4882a593Smuzhiyun __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun .endm 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun .macro ___flush_invalidate_dcache_all ar at 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 103*4882a593Smuzhiyun __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 104*4882a593Smuzhiyun #endif 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun .endm 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun .macro ___flush_dcache_all ar at 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 112*4882a593Smuzhiyun __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 113*4882a593Smuzhiyun #endif 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun .endm 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun .macro ___invalidate_dcache_all ar at 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 121*4882a593Smuzhiyun __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ 122*4882a593Smuzhiyun XCHAL_DCACHE_LINEWIDTH 123*4882a593Smuzhiyun #endif 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun .endm 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun .macro ___invalidate_icache_all ar at 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #if XCHAL_ICACHE_SIZE 131*4882a593Smuzhiyun __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ 132*4882a593Smuzhiyun XCHAL_ICACHE_LINEWIDTH 133*4882a593Smuzhiyun #endif 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun .endm 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun .macro ___flush_invalidate_dcache_range ar as at 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 142*4882a593Smuzhiyun __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH 143*4882a593Smuzhiyun #endif 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun .endm 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun .macro ___flush_dcache_range ar as at 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 151*4882a593Smuzhiyun __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH 152*4882a593Smuzhiyun #endif 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun .endm 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun .macro ___invalidate_dcache_range ar as at 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 160*4882a593Smuzhiyun __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH 161*4882a593Smuzhiyun #endif 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun .endm 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun .macro ___invalidate_icache_range ar as at 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #if XCHAL_ICACHE_SIZE 169*4882a593Smuzhiyun __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH 170*4882a593Smuzhiyun #endif 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun .endm 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun .macro ___flush_invalidate_dcache_page ar as 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 179*4882a593Smuzhiyun __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 180*4882a593Smuzhiyun #endif 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun .endm 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun .macro ___flush_dcache_page ar as 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 188*4882a593Smuzhiyun __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 189*4882a593Smuzhiyun #endif 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun .endm 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun .macro ___invalidate_dcache_page ar as 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #if XCHAL_DCACHE_SIZE 197*4882a593Smuzhiyun __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 198*4882a593Smuzhiyun #endif 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun .endm 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun .macro ___invalidate_icache_page ar as 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #if XCHAL_ICACHE_SIZE 206*4882a593Smuzhiyun __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 207*4882a593Smuzhiyun #endif 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun .endm 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #endif /* _XTENSA_CACHEASM_H */ 212