1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Tensilica Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _XTENSA_CACHE_H 7*4882a593Smuzhiyun #define _XTENSA_CACHE_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/arch/core.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun void __flush_dcache_all(void); 16*4882a593Smuzhiyun void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size); 17*4882a593Smuzhiyun void __invalidate_dcache_all(void); 18*4882a593Smuzhiyun void __invalidate_dcache_range(unsigned long addr, unsigned long size); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun void __invalidate_icache_all(void); 21*4882a593Smuzhiyun void __invalidate_icache_range(unsigned long addr, unsigned long size); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* _XTENSA_CACHE_H */ 26