1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Based on Linux/Xtensa kernel version
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2001 - 2007 Tensilica Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef _XTENSA_BYTEORDER_H
10*4882a593Smuzhiyun #define _XTENSA_BYTEORDER_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/types.h>
13*4882a593Smuzhiyun
___arch__swab32(__u32 x)14*4882a593Smuzhiyun static inline __attribute__((const)) __u32 ___arch__swab32(__u32 x)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun __u32 res;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* instruction sequence from Xtensa ISA release 2/2000 */
19*4882a593Smuzhiyun __asm__("ssai 8\n\t"
20*4882a593Smuzhiyun "srli %0, %1, 16\n\t"
21*4882a593Smuzhiyun "src %0, %0, %1\n\t"
22*4882a593Smuzhiyun "src %0, %0, %0\n\t"
23*4882a593Smuzhiyun "src %0, %1, %0\n"
24*4882a593Smuzhiyun : "=&a" (res)
25*4882a593Smuzhiyun : "a" (x)
26*4882a593Smuzhiyun );
27*4882a593Smuzhiyun return res;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
___arch__swab16(__u16 x)30*4882a593Smuzhiyun static inline __attribute__((const)) __u16 ___arch__swab16(__u16 x)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * Given that 'short' values are signed (i.e., can be negative),
34*4882a593Smuzhiyun * we cannot assume that the upper 16-bits of the register are
35*4882a593Smuzhiyun * zero. We are careful to mask values after shifting.
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
40*4882a593Smuzhiyun * inserts an extui instruction after putting this function inline
41*4882a593Smuzhiyun * to ensure that it uses only the least-significant 16 bits of
42*4882a593Smuzhiyun * the result. xt-xcc doesn't use an extui, but assumes the
43*4882a593Smuzhiyun * __asm__ macro follows convention that the upper 16 bits of an
44*4882a593Smuzhiyun * 'unsigned short' result are still zero. This macro doesn't
45*4882a593Smuzhiyun * follow convention; indeed, it leaves garbage in the upport 16
46*4882a593Smuzhiyun * bits of the register.
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
49*4882a593Smuzhiyun * types while the return type of the function is a 16-bit type
50*4882a593Smuzhiyun * forces both compilers to insert exactly one extui instruction
51*4882a593Smuzhiyun * (or equivalent) to mask off the upper 16 bits.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun __u32 res;
55*4882a593Smuzhiyun __u32 tmp;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun __asm__("extui %1, %2, 8, 8\n\t"
58*4882a593Smuzhiyun "slli %0, %2, 8\n\t"
59*4882a593Smuzhiyun "or %0, %0, %1\n"
60*4882a593Smuzhiyun : "=&a" (res), "=&a" (tmp)
61*4882a593Smuzhiyun : "a" (x)
62*4882a593Smuzhiyun );
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return res;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define __arch__swab32(x) ___arch__swab32(x)
68*4882a593Smuzhiyun #define __arch__swab16(x) ___arch__swab16(x)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
71*4882a593Smuzhiyun # define __BYTEORDER_HAS_U64__
72*4882a593Smuzhiyun # define __SWAB_64_THRU_32__
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #ifdef __XTENSA_EL__
76*4882a593Smuzhiyun # include <linux/byteorder/little_endian.h>
77*4882a593Smuzhiyun #elif defined(__XTENSA_EB__)
78*4882a593Smuzhiyun # include <linux/byteorder/big_endian.h>
79*4882a593Smuzhiyun #else
80*4882a593Smuzhiyun # error processor byte order undefined!
81*4882a593Smuzhiyun #endif
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #endif /* _XTENSA_BYTEORDER_H */
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