1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header file describes this specific Xtensa processor's TIE extensions 3*4882a593Smuzhiyun * that extend basic Xtensa core functionality. It is customized to this 4*4882a593Smuzhiyun * Xtensa processor configuration. 5*4882a593Smuzhiyun * This file is autogenerated, please do not edit. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 1999-2010 Tensilica Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _XTENSA_CORE_TIE_H 13*4882a593Smuzhiyun #define _XTENSA_CORE_TIE_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define XCHAL_CP_NUM 1 /* number of coprocessors */ 16*4882a593Smuzhiyun #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */ 17*4882a593Smuzhiyun #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */ 18*4882a593Smuzhiyun #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Basic parameters of each coprocessor: */ 21*4882a593Smuzhiyun #define XCHAL_CP7_NAME "XTIOP" 22*4882a593Smuzhiyun #define XCHAL_CP7_IDENT XTIOP 23*4882a593Smuzhiyun #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */ 24*4882a593Smuzhiyun #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */ 25*4882a593Smuzhiyun #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 28*4882a593Smuzhiyun #define XCHAL_CP0_SA_SIZE 0 29*4882a593Smuzhiyun #define XCHAL_CP0_SA_ALIGN 1 30*4882a593Smuzhiyun #define XCHAL_CP1_SA_SIZE 0 31*4882a593Smuzhiyun #define XCHAL_CP1_SA_ALIGN 1 32*4882a593Smuzhiyun #define XCHAL_CP2_SA_SIZE 0 33*4882a593Smuzhiyun #define XCHAL_CP2_SA_ALIGN 1 34*4882a593Smuzhiyun #define XCHAL_CP3_SA_SIZE 0 35*4882a593Smuzhiyun #define XCHAL_CP3_SA_ALIGN 1 36*4882a593Smuzhiyun #define XCHAL_CP4_SA_SIZE 0 37*4882a593Smuzhiyun #define XCHAL_CP4_SA_ALIGN 1 38*4882a593Smuzhiyun #define XCHAL_CP5_SA_SIZE 0 39*4882a593Smuzhiyun #define XCHAL_CP5_SA_ALIGN 1 40*4882a593Smuzhiyun #define XCHAL_CP6_SA_SIZE 0 41*4882a593Smuzhiyun #define XCHAL_CP6_SA_ALIGN 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Save area for non-coprocessor optional and custom (TIE) state: */ 44*4882a593Smuzhiyun #define XCHAL_NCP_SA_SIZE 32 45*4882a593Smuzhiyun #define XCHAL_NCP_SA_ALIGN 4 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Total save area for optional and custom state (NCP + CPn): */ 48*4882a593Smuzhiyun #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ 49*4882a593Smuzhiyun #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Detailed contents of save areas. 53*4882a593Smuzhiyun * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 54*4882a593Smuzhiyun * before expanding the XCHAL_xxx_SA_LIST() macros. 55*4882a593Smuzhiyun * 56*4882a593Smuzhiyun * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 57*4882a593Smuzhiyun * dbnum,base,regnum,bitsz,gapsz,reset,x...) 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * s = passed from XCHAL_*_LIST(s), eg. to select how to expand 60*4882a593Smuzhiyun * ccused = set if used by compiler without special options or code 61*4882a593Smuzhiyun * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) 62*4882a593Smuzhiyun * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) 63*4882a593Smuzhiyun * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) 64*4882a593Smuzhiyun * name = lowercase reg name (no quotes) 65*4882a593Smuzhiyun * galign = group byte alignment (power of 2) (galign >= align) 66*4882a593Smuzhiyun * align = register byte alignment (power of 2) 67*4882a593Smuzhiyun * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) 68*4882a593Smuzhiyun * (not including any pad bytes required to galign this or next reg) 69*4882a593Smuzhiyun * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) 70*4882a593Smuzhiyun * base = reg shortname w/o index (or sr=special, ur=TIE user reg) 71*4882a593Smuzhiyun * regnum = reg index in regfile, or special/TIE-user reg number 72*4882a593Smuzhiyun * bitsz = number of significant bits (regfile width, or ur/sr mask bits) 73*4882a593Smuzhiyun * gapsz = intervening bits, if bitsz bits not stored contiguously 74*4882a593Smuzhiyun * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) 75*4882a593Smuzhiyun * reset = register reset value (or 0 if undefined at reset) 76*4882a593Smuzhiyun * x = reserved for future use (0 until then) 77*4882a593Smuzhiyun * 78*4882a593Smuzhiyun * To filter out certain registers, e.g. to expand only the non-global 79*4882a593Smuzhiyun * registers used by the compiler, you can do something like this: 80*4882a593Smuzhiyun * 81*4882a593Smuzhiyun * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 82*4882a593Smuzhiyun * #define SELCC0(p...) 83*4882a593Smuzhiyun * #define SELCC1(abikind,p...) SELAK##abikind(p) 84*4882a593Smuzhiyun * #define SELAK0(p...) REG(p) 85*4882a593Smuzhiyun * #define SELAK1(p...) REG(p) 86*4882a593Smuzhiyun * #define SELAK2(p...) 87*4882a593Smuzhiyun * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ 88*4882a593Smuzhiyun * ...what you want to expand... 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define XCHAL_NCP_SA_NUM 8 92*4882a593Smuzhiyun #define XCHAL_NCP_SA_LIST(s) \ 93*4882a593Smuzhiyun XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ 94*4882a593Smuzhiyun XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 95*4882a593Smuzhiyun XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 96*4882a593Smuzhiyun XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 97*4882a593Smuzhiyun XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 98*4882a593Smuzhiyun XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 99*4882a593Smuzhiyun XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ 100*4882a593Smuzhiyun XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define XCHAL_CP0_SA_NUM 0 103*4882a593Smuzhiyun #define XCHAL_CP0_SA_LIST(s) /* empty */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define XCHAL_CP1_SA_NUM 0 106*4882a593Smuzhiyun #define XCHAL_CP1_SA_LIST(s) /* empty */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define XCHAL_CP2_SA_NUM 0 109*4882a593Smuzhiyun #define XCHAL_CP2_SA_LIST(s) /* empty */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define XCHAL_CP3_SA_NUM 0 112*4882a593Smuzhiyun #define XCHAL_CP3_SA_LIST(s) /* empty */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define XCHAL_CP4_SA_NUM 0 115*4882a593Smuzhiyun #define XCHAL_CP4_SA_LIST(s) /* empty */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define XCHAL_CP5_SA_NUM 0 118*4882a593Smuzhiyun #define XCHAL_CP5_SA_LIST(s) /* empty */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define XCHAL_CP6_SA_NUM 0 121*4882a593Smuzhiyun #define XCHAL_CP6_SA_LIST(s) /* empty */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define XCHAL_CP7_SA_NUM 0 124*4882a593Smuzhiyun #define XCHAL_CP7_SA_LIST(s) /* empty */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 127*4882a593Smuzhiyun #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif /*_XTENSA_CORE_TIE_H*/ 130*4882a593Smuzhiyun 131