1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This header file contains assembly-language definitions (assembly 3*4882a593Smuzhiyun * macros, etc.) for this specific Xtensa processor's TIE extensions 4*4882a593Smuzhiyun * and options. It is customized to this Xtensa processor configuration. 5*4882a593Smuzhiyun * This file is autogenerated, please do not edit. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 1999-2007 Tensilica Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _XTENSA_CORE_TIE_ASM_H 13*4882a593Smuzhiyun #define _XTENSA_CORE_TIE_ASM_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Selection parameter values for save-area save/restore macros: */ 16*4882a593Smuzhiyun /* Option vs. TIE: */ 17*4882a593Smuzhiyun #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 18*4882a593Smuzhiyun #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 19*4882a593Smuzhiyun /* Whether used automatically by compiler: */ 20*4882a593Smuzhiyun #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 21*4882a593Smuzhiyun #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 22*4882a593Smuzhiyun /* ABI handling across function calls: */ 23*4882a593Smuzhiyun #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 24*4882a593Smuzhiyun #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 25*4882a593Smuzhiyun #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 26*4882a593Smuzhiyun /* Misc */ 27*4882a593Smuzhiyun #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Macro to save all non-coprocessor (extra) custom TIE and optional state 32*4882a593Smuzhiyun * (not including zero-overhead loop registers). 33*4882a593Smuzhiyun * Save area ptr (clobbered): ptr (1 byte aligned) 34*4882a593Smuzhiyun * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 37*4882a593Smuzhiyun xchal_sa_start \continue, \ofs 38*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 39*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-8, 4, 4 40*4882a593Smuzhiyun rsr \at1, ACCLO // MAC16 accumulator 41*4882a593Smuzhiyun rsr \at2, ACCHI 42*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 43*4882a593Smuzhiyun s32i \at2, \ptr, .Lxchal_ofs_ + 4 44*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 45*4882a593Smuzhiyun .endif 46*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 47*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-16, 4, 4 48*4882a593Smuzhiyun rsr \at1, M0 // MAC16 registers 49*4882a593Smuzhiyun rsr \at2, M1 50*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 51*4882a593Smuzhiyun s32i \at2, \ptr, .Lxchal_ofs_ + 4 52*4882a593Smuzhiyun rsr \at1, M2 53*4882a593Smuzhiyun rsr \at2, M3 54*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 8 55*4882a593Smuzhiyun s32i \at2, \ptr, .Lxchal_ofs_ + 12 56*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 57*4882a593Smuzhiyun .endif 58*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 59*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 60*4882a593Smuzhiyun rsr \at1, SCOMPARE1 // conditional store option 61*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 62*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 63*4882a593Smuzhiyun .endif 64*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 65*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 66*4882a593Smuzhiyun rur \at1, THREADPTR // threadptr option 67*4882a593Smuzhiyun s32i \at1, \ptr, .Lxchal_ofs_ + 0 68*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 69*4882a593Smuzhiyun .endif 70*4882a593Smuzhiyun .endm // xchal_ncp_store 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Macro to save all non-coprocessor (extra) custom TIE and optional state 73*4882a593Smuzhiyun * (not including zero-overhead loop registers). 74*4882a593Smuzhiyun * Save area ptr (clobbered): ptr (1 byte aligned) 75*4882a593Smuzhiyun * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 78*4882a593Smuzhiyun xchal_sa_start \continue, \ofs 79*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 80*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-8, 4, 4 81*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 82*4882a593Smuzhiyun l32i \at2, \ptr, .Lxchal_ofs_ + 4 83*4882a593Smuzhiyun wsr \at1, ACCLO // MAC16 accumulator 84*4882a593Smuzhiyun wsr \at2, ACCHI 85*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 86*4882a593Smuzhiyun .endif 87*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 88*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-16, 4, 4 89*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 90*4882a593Smuzhiyun l32i \at2, \ptr, .Lxchal_ofs_ + 4 91*4882a593Smuzhiyun wsr \at1, M0 // MAC16 registers 92*4882a593Smuzhiyun wsr \at2, M1 93*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 8 94*4882a593Smuzhiyun l32i \at2, \ptr, .Lxchal_ofs_ + 12 95*4882a593Smuzhiyun wsr \at1, M2 96*4882a593Smuzhiyun wsr \at2, M3 97*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 98*4882a593Smuzhiyun .endif 99*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 100*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 101*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 102*4882a593Smuzhiyun wsr \at1, SCOMPARE1 // conditional store option 103*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 104*4882a593Smuzhiyun .endif 105*4882a593Smuzhiyun .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 106*4882a593Smuzhiyun xchal_sa_align \ptr, 0, 1024-4, 4, 4 107*4882a593Smuzhiyun l32i \at1, \ptr, .Lxchal_ofs_ + 0 108*4882a593Smuzhiyun wur \at1, THREADPTR // threadptr option 109*4882a593Smuzhiyun .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 110*4882a593Smuzhiyun .endif 111*4882a593Smuzhiyun .endm // xchal_ncp_load 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define XCHAL_NCP_NUM_ATMPS 2 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define XCHAL_SA_NUM_ATMPS 2 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /*_XTENSA_CORE_TIE_ASM_H*/ 121*4882a593Smuzhiyun 122