1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2008-2013 Tensilica Inc. 3*4882a593Smuzhiyun * Copyright (C) 2016 Cadence Design Systems Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _XTENSA_ADDRSPACE_H 9*4882a593Smuzhiyun #define _XTENSA_ADDRSPACE_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/arch/core.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * MMU Memory Map 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * noMMU and v3 MMU have identity mapped address space on reset. 17*4882a593Smuzhiyun * V2 MMU: 18*4882a593Smuzhiyun * IO (uncached) f0000000..ffffffff -> f000000 19*4882a593Smuzhiyun * IO (cached) e0000000..efffffff -> f000000 20*4882a593Smuzhiyun * MEM (uncached) d8000000..dfffffff -> 0000000 21*4882a593Smuzhiyun * MEM (cached) d0000000..d7ffffff -> 0000000 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * The actual location of memory and IO is the board property. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) 27*4882a593Smuzhiyun #define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) 28*4882a593Smuzhiyun #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ 29*4882a593Smuzhiyun XCHAL_VECBASE_RESET_PADDR) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif /* _XTENSA_ADDRSPACE_H */ 32