1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Intel Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Intel Mobile Internet Devices (MID) based on Intel Atom SoCs have few
5*4882a593Smuzhiyun * microcontrollers inside to do some auxiliary tasks. One of such
6*4882a593Smuzhiyun * microcontroller is System Controller Unit (SCU) which, in particular,
7*4882a593Smuzhiyun * is servicing watchdog and controlling system reset function.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This driver enables IPC channel to SCU.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <dm.h>
15*4882a593Smuzhiyun #include <regmap.h>
16*4882a593Smuzhiyun #include <syscon.h>
17*4882a593Smuzhiyun #include <asm/cpu.h>
18*4882a593Smuzhiyun #include <asm/scu.h>
19*4882a593Smuzhiyun #include <linux/errno.h>
20*4882a593Smuzhiyun #include <linux/io.h>
21*4882a593Smuzhiyun #include <linux/kernel.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* SCU register map */
24*4882a593Smuzhiyun struct ipc_regs {
25*4882a593Smuzhiyun u32 cmd;
26*4882a593Smuzhiyun u32 status;
27*4882a593Smuzhiyun u32 sptr;
28*4882a593Smuzhiyun u32 dptr;
29*4882a593Smuzhiyun u32 reserved[28];
30*4882a593Smuzhiyun u32 wbuf[4];
31*4882a593Smuzhiyun u32 rbuf[4];
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct scu {
35*4882a593Smuzhiyun struct ipc_regs *regs;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /**
39*4882a593Smuzhiyun * scu_ipc_send_command() - send command to SCU
40*4882a593Smuzhiyun * @regs: register map of SCU
41*4882a593Smuzhiyun * @cmd: command
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun * Command Register (Write Only):
44*4882a593Smuzhiyun * A write to this register results in an interrupt to the SCU core processor
45*4882a593Smuzhiyun * Format:
46*4882a593Smuzhiyun * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
47*4882a593Smuzhiyun */
scu_ipc_send_command(struct ipc_regs * regs,u32 cmd)48*4882a593Smuzhiyun static void scu_ipc_send_command(struct ipc_regs *regs, u32 cmd)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun writel(cmd, ®s->cmd);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /**
54*4882a593Smuzhiyun * scu_ipc_check_status() - check status of last command
55*4882a593Smuzhiyun * @regs: register map of SCU
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * Status Register (Read Only):
58*4882a593Smuzhiyun * Driver will read this register to get the ready/busy status of the IPC
59*4882a593Smuzhiyun * block and error status of the IPC command that was just processed by SCU
60*4882a593Smuzhiyun * Format:
61*4882a593Smuzhiyun * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
62*4882a593Smuzhiyun */
scu_ipc_check_status(struct ipc_regs * regs)63*4882a593Smuzhiyun static int scu_ipc_check_status(struct ipc_regs *regs)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun int loop_count = 100000;
66*4882a593Smuzhiyun int status;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun do {
69*4882a593Smuzhiyun status = readl(®s->status);
70*4882a593Smuzhiyun if (!(status & BIT(0)))
71*4882a593Smuzhiyun break;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun udelay(1);
74*4882a593Smuzhiyun } while (--loop_count);
75*4882a593Smuzhiyun if (!loop_count)
76*4882a593Smuzhiyun return -ETIMEDOUT;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (status & BIT(1)) {
79*4882a593Smuzhiyun printf("%s() status=0x%08x\n", __func__, status);
80*4882a593Smuzhiyun return -EIO;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
scu_ipc_cmd(struct ipc_regs * regs,u32 cmd,u32 sub,u32 * in,int inlen,u32 * out,int outlen)86*4882a593Smuzhiyun static int scu_ipc_cmd(struct ipc_regs *regs, u32 cmd, u32 sub,
87*4882a593Smuzhiyun u32 *in, int inlen, u32 *out, int outlen)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun int i, err;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun for (i = 0; i < inlen; i++)
92*4882a593Smuzhiyun writel(*in++, ®s->wbuf[i]);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun scu_ipc_send_command(regs, (inlen << 16) | (sub << 12) | cmd);
95*4882a593Smuzhiyun err = scu_ipc_check_status(regs);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!err) {
98*4882a593Smuzhiyun for (i = 0; i < outlen; i++)
99*4882a593Smuzhiyun *out++ = readl(®s->rbuf[i]);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return err;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /**
106*4882a593Smuzhiyun * scu_ipc_simple_command() - send a simple command
107*4882a593Smuzhiyun * @cmd: command
108*4882a593Smuzhiyun * @sub: sub type
109*4882a593Smuzhiyun *
110*4882a593Smuzhiyun * Issue a simple command to the SCU. Do not use this interface if
111*4882a593Smuzhiyun * you must then access data as any data values may be overwritten
112*4882a593Smuzhiyun * by another SCU access by the time this function returns.
113*4882a593Smuzhiyun *
114*4882a593Smuzhiyun * This function may sleep. Locking for SCU accesses is handled for
115*4882a593Smuzhiyun * the caller.
116*4882a593Smuzhiyun */
scu_ipc_simple_command(u32 cmd,u32 sub)117*4882a593Smuzhiyun int scu_ipc_simple_command(u32 cmd, u32 sub)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun struct scu *scu;
120*4882a593Smuzhiyun struct udevice *dev;
121*4882a593Smuzhiyun int ret;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun ret = syscon_get_by_driver_data(X86_SYSCON_SCU, &dev);
124*4882a593Smuzhiyun if (ret)
125*4882a593Smuzhiyun return ret;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun scu = dev_get_priv(dev);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun scu_ipc_send_command(scu->regs, sub << 12 | cmd);
130*4882a593Smuzhiyun return scu_ipc_check_status(scu->regs);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
scu_ipc_command(u32 cmd,u32 sub,u32 * in,int inlen,u32 * out,int outlen)133*4882a593Smuzhiyun int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct scu *scu;
136*4882a593Smuzhiyun struct udevice *dev;
137*4882a593Smuzhiyun int ret;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun ret = syscon_get_by_driver_data(X86_SYSCON_SCU, &dev);
140*4882a593Smuzhiyun if (ret)
141*4882a593Smuzhiyun return ret;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun scu = dev_get_priv(dev);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return scu_ipc_cmd(scu->regs, cmd, sub, in, inlen, out, outlen);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
scu_ipc_probe(struct udevice * dev)148*4882a593Smuzhiyun static int scu_ipc_probe(struct udevice *dev)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct scu *scu = dev_get_priv(dev);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun scu->regs = syscon_get_first_range(X86_SYSCON_SCU);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const struct udevice_id scu_ipc_match[] = {
158*4882a593Smuzhiyun { .compatible = "intel,scu-ipc", .data = X86_SYSCON_SCU },
159*4882a593Smuzhiyun { /* sentinel */ }
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun U_BOOT_DRIVER(scu_ipc) = {
163*4882a593Smuzhiyun .name = "scu_ipc",
164*4882a593Smuzhiyun .id = UCLASS_SYSCON,
165*4882a593Smuzhiyun .of_match = scu_ipc_match,
166*4882a593Smuzhiyun .probe = scu_ipc_probe,
167*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct scu),
168*4882a593Smuzhiyun };
169