1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2014 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * From Coreboot src/lib/ramtest.c
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/post.h>
12*4882a593Smuzhiyun
write_phys(unsigned long addr,u32 value)13*4882a593Smuzhiyun static void write_phys(unsigned long addr, u32 value)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun #if CONFIG_SSE2
16*4882a593Smuzhiyun asm volatile(
17*4882a593Smuzhiyun "movnti %1, (%0)"
18*4882a593Smuzhiyun : /* outputs */
19*4882a593Smuzhiyun : "r" (addr), "r" (value) /* inputs */
20*4882a593Smuzhiyun : /* clobbers */
21*4882a593Smuzhiyun );
22*4882a593Smuzhiyun #else
23*4882a593Smuzhiyun writel(value, addr);
24*4882a593Smuzhiyun #endif
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
read_phys(unsigned long addr)27*4882a593Smuzhiyun static u32 read_phys(unsigned long addr)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun return readl(addr);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
phys_memory_barrier(void)32*4882a593Smuzhiyun static void phys_memory_barrier(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun #if CONFIG_SSE2
35*4882a593Smuzhiyun /* Needed for movnti */
36*4882a593Smuzhiyun asm volatile(
37*4882a593Smuzhiyun "sfence"
38*4882a593Smuzhiyun :
39*4882a593Smuzhiyun :
40*4882a593Smuzhiyun : "memory"
41*4882a593Smuzhiyun );
42*4882a593Smuzhiyun #else
43*4882a593Smuzhiyun asm volatile(""
44*4882a593Smuzhiyun :
45*4882a593Smuzhiyun :
46*4882a593Smuzhiyun : "memory");
47*4882a593Smuzhiyun #endif
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
quick_ram_check(void)50*4882a593Smuzhiyun void quick_ram_check(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int fail = 0;
53*4882a593Smuzhiyun u32 backup;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun backup = read_phys(CONFIG_RAMBASE);
56*4882a593Smuzhiyun write_phys(CONFIG_RAMBASE, 0x55555555);
57*4882a593Smuzhiyun phys_memory_barrier();
58*4882a593Smuzhiyun if (read_phys(CONFIG_RAMBASE) != 0x55555555)
59*4882a593Smuzhiyun fail = 1;
60*4882a593Smuzhiyun write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
61*4882a593Smuzhiyun phys_memory_barrier();
62*4882a593Smuzhiyun if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
63*4882a593Smuzhiyun fail = 1;
64*4882a593Smuzhiyun write_phys(CONFIG_RAMBASE, 0x00000000);
65*4882a593Smuzhiyun phys_memory_barrier();
66*4882a593Smuzhiyun if (read_phys(CONFIG_RAMBASE) != 0x00000000)
67*4882a593Smuzhiyun fail = 1;
68*4882a593Smuzhiyun write_phys(CONFIG_RAMBASE, 0xffffffff);
69*4882a593Smuzhiyun phys_memory_barrier();
70*4882a593Smuzhiyun if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
71*4882a593Smuzhiyun fail = 1;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun write_phys(CONFIG_RAMBASE, backup);
74*4882a593Smuzhiyun if (fail) {
75*4882a593Smuzhiyun post_code(POST_RAM_FAILURE);
76*4882a593Smuzhiyun panic("RAM INIT FAILURE!\n");
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun phys_memory_barrier();
79*4882a593Smuzhiyun }
80