1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Intel Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <regmap.h>
9*4882a593Smuzhiyun #include <syscon.h>
10*4882a593Smuzhiyun #include <asm/cpu.h>
11*4882a593Smuzhiyun #include <asm/pmu.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Registers */
16*4882a593Smuzhiyun struct pmu_regs {
17*4882a593Smuzhiyun u32 sts;
18*4882a593Smuzhiyun u32 cmd;
19*4882a593Smuzhiyun u32 ics;
20*4882a593Smuzhiyun u32 reserved;
21*4882a593Smuzhiyun u32 wkc[4];
22*4882a593Smuzhiyun u32 wks[4];
23*4882a593Smuzhiyun u32 ssc[4];
24*4882a593Smuzhiyun u32 sss[4];
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Bits in PMU_REGS_STS */
28*4882a593Smuzhiyun #define PMU_REGS_STS_BUSY (1 << 8)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct pmu_mid {
31*4882a593Smuzhiyun struct pmu_regs *regs;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
pmu_read_status(struct pmu_regs * regs)34*4882a593Smuzhiyun static int pmu_read_status(struct pmu_regs *regs)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun int retry = 500000;
37*4882a593Smuzhiyun u32 val;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun do {
40*4882a593Smuzhiyun val = readl(®s->sts);
41*4882a593Smuzhiyun if (!(val & PMU_REGS_STS_BUSY))
42*4882a593Smuzhiyun return 0;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun udelay(1);
45*4882a593Smuzhiyun } while (--retry);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun printf("WARNING: PMU still busy\n");
48*4882a593Smuzhiyun return -EBUSY;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
pmu_power_lss(struct pmu_regs * regs,unsigned int lss,bool on)51*4882a593Smuzhiyun static int pmu_power_lss(struct pmu_regs *regs, unsigned int lss, bool on)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun unsigned int offset = (lss * 2) / 32;
54*4882a593Smuzhiyun unsigned int shift = (lss * 2) % 32;
55*4882a593Smuzhiyun u32 ssc;
56*4882a593Smuzhiyun int ret;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Check PMU status */
59*4882a593Smuzhiyun ret = pmu_read_status(regs);
60*4882a593Smuzhiyun if (ret)
61*4882a593Smuzhiyun return ret;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Read PMU values */
64*4882a593Smuzhiyun ssc = readl(®s->sss[offset]);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Modify PMU values */
67*4882a593Smuzhiyun if (on)
68*4882a593Smuzhiyun ssc &= ~(0x3 << shift); /* D0 */
69*4882a593Smuzhiyun else
70*4882a593Smuzhiyun ssc |= 0x3 << shift; /* D3hot */
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Write modified PMU values */
73*4882a593Smuzhiyun writel(ssc, ®s->ssc[offset]);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Update modified PMU values */
76*4882a593Smuzhiyun writel(0x00002201, ®s->cmd);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Check PMU status */
79*4882a593Smuzhiyun return pmu_read_status(regs);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
pmu_turn_power(unsigned int lss,bool on)82*4882a593Smuzhiyun int pmu_turn_power(unsigned int lss, bool on)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct pmu_mid *pmu;
85*4882a593Smuzhiyun struct udevice *dev;
86*4882a593Smuzhiyun int ret;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun ret = syscon_get_by_driver_data(X86_SYSCON_PMU, &dev);
89*4882a593Smuzhiyun if (ret)
90*4882a593Smuzhiyun return ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun pmu = dev_get_priv(dev);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return pmu_power_lss(pmu->regs, lss, on);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
pmu_mid_probe(struct udevice * dev)97*4882a593Smuzhiyun static int pmu_mid_probe(struct udevice *dev)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct pmu_mid *pmu = dev_get_priv(dev);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun pmu->regs = syscon_get_first_range(X86_SYSCON_PMU);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static const struct udevice_id pmu_mid_match[] = {
107*4882a593Smuzhiyun { .compatible = "intel,pmu-mid", .data = X86_SYSCON_PMU },
108*4882a593Smuzhiyun { /* sentinel */ }
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun U_BOOT_DRIVER(intel_mid_pmu) = {
112*4882a593Smuzhiyun .name = "pmu_mid",
113*4882a593Smuzhiyun .id = UCLASS_SYSCON,
114*4882a593Smuzhiyun .of_match = pmu_mid_match,
115*4882a593Smuzhiyun .probe = pmu_mid_probe,
116*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct pmu_mid),
117*4882a593Smuzhiyun };
118