1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009
3*4882a593Smuzhiyun * Graeme Russ, <graeme.russ@gmail.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2002
6*4882a593Smuzhiyun * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun * This file provides the interrupt handling functionality for systems
13*4882a593Smuzhiyun * based on the standard PC/AT architecture using two cascaded i8259
14*4882a593Smuzhiyun * Programmable Interrupt Controllers.
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun #include <asm/i8259.h>
20*4882a593Smuzhiyun #include <asm/ibmpc.h>
21*4882a593Smuzhiyun #include <asm/interrupt.h>
22*4882a593Smuzhiyun
i8259_init(void)23*4882a593Smuzhiyun int i8259_init(void)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun u8 i;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Mask all interrupts */
28*4882a593Smuzhiyun outb(0xff, MASTER_PIC + IMR);
29*4882a593Smuzhiyun outb(0xff, SLAVE_PIC + IMR);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Master PIC
33*4882a593Smuzhiyun * Place master PIC interrupts at INT20
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
36*4882a593Smuzhiyun outb(0x20, MASTER_PIC + ICW2);
37*4882a593Smuzhiyun outb(IR2, MASTER_PIC + ICW3);
38*4882a593Smuzhiyun outb(ICW4_PM, MASTER_PIC + ICW4);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun for (i = 0; i < 8; i++)
41*4882a593Smuzhiyun outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * Slave PIC
45*4882a593Smuzhiyun * Place slave PIC interrupts at INT28
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
48*4882a593Smuzhiyun outb(0x28, SLAVE_PIC + ICW2);
49*4882a593Smuzhiyun outb(0x02, SLAVE_PIC + ICW3);
50*4882a593Smuzhiyun outb(ICW4_PM, SLAVE_PIC + ICW4);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun for (i = 0; i < 8; i++)
53*4882a593Smuzhiyun outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Enable cascaded interrupts by unmasking the cascade IRQ pin of
57*4882a593Smuzhiyun * the master PIC
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun unmask_irq(2);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Interrupt 9 should be level triggered (SCI). The OS might do this */
62*4882a593Smuzhiyun configure_irq_trigger(9, true);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
mask_irq(int irq)67*4882a593Smuzhiyun void mask_irq(int irq)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun int imr_port;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if (irq >= SYS_NUM_IRQS)
72*4882a593Smuzhiyun return;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if (irq > 7)
75*4882a593Smuzhiyun imr_port = SLAVE_PIC + IMR;
76*4882a593Smuzhiyun else
77*4882a593Smuzhiyun imr_port = MASTER_PIC + IMR;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
unmask_irq(int irq)82*4882a593Smuzhiyun void unmask_irq(int irq)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun int imr_port;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (irq >= SYS_NUM_IRQS)
87*4882a593Smuzhiyun return;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (irq > 7)
90*4882a593Smuzhiyun imr_port = SLAVE_PIC + IMR;
91*4882a593Smuzhiyun else
92*4882a593Smuzhiyun imr_port = MASTER_PIC + IMR;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
specific_eoi(int irq)97*4882a593Smuzhiyun void specific_eoi(int irq)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun if (irq >= SYS_NUM_IRQS)
100*4882a593Smuzhiyun return;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (irq > 7) {
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun * IRQ is on the slave - Issue a corresponding EOI to the
105*4882a593Smuzhiyun * slave PIC and an EOI for IRQ2 (the cascade interrupt)
106*4882a593Smuzhiyun * on the master PIC
107*4882a593Smuzhiyun */
108*4882a593Smuzhiyun outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
109*4882a593Smuzhiyun irq = SEOI_IR2;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
configure_irq_trigger(int int_num,bool is_level_triggered)115*4882a593Smuzhiyun void configure_irq_trigger(int int_num, bool is_level_triggered)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
120*4882a593Smuzhiyun if (is_level_triggered)
121*4882a593Smuzhiyun int_bits |= (1 << int_num);
122*4882a593Smuzhiyun else
123*4882a593Smuzhiyun int_bits &= ~(1 << int_num);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* Write new values */
126*4882a593Smuzhiyun debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
127*4882a593Smuzhiyun outb((u8)(int_bits & 0xff), ELCR1);
128*4882a593Smuzhiyun outb((u8)(int_bits >> 8), ELCR2);
129*4882a593Smuzhiyun }
130