1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/fsp/fsp_support.h> 9*4882a593Smuzhiyun #include <asm/e820.h> 10*4882a593Smuzhiyun #include <asm/mrccache.h> 11*4882a593Smuzhiyun #include <asm/post.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 14*4882a593Smuzhiyun dram_init(void)15*4882a593Smuzhiyunint dram_init(void) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun phys_size_t ram_size = 0; 18*4882a593Smuzhiyun const struct hob_header *hdr; 19*4882a593Smuzhiyun struct hob_res_desc *res_desc; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun hdr = gd->arch.hob_list; 22*4882a593Smuzhiyun while (!end_of_hob(hdr)) { 23*4882a593Smuzhiyun if (hdr->type == HOB_TYPE_RES_DESC) { 24*4882a593Smuzhiyun res_desc = (struct hob_res_desc *)hdr; 25*4882a593Smuzhiyun if (res_desc->type == RES_SYS_MEM || 26*4882a593Smuzhiyun res_desc->type == RES_MEM_RESERVED) { 27*4882a593Smuzhiyun ram_size += res_desc->len; 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun hdr = get_next_hob(hdr); 31*4882a593Smuzhiyun } 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun gd->ram_size = ram_size; 34*4882a593Smuzhiyun post_code(POST_DRAM); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #ifdef CONFIG_ENABLE_MRC_CACHE 37*4882a593Smuzhiyun gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, 38*4882a593Smuzhiyun &gd->arch.mrc_output_len); 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun return 0; 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun dram_init_banksize(void)44*4882a593Smuzhiyunint dram_init_banksize(void) 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun gd->bd->bi_dram[0].start = 0; 47*4882a593Smuzhiyun gd->bd->bi_dram[0].size = gd->ram_size; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun return 0; 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * This function looks for the highest region of memory lower than 4GB which 54*4882a593Smuzhiyun * has enough space for U-Boot where U-Boot is aligned on a page boundary. 55*4882a593Smuzhiyun * It overrides the default implementation found elsewhere which simply 56*4882a593Smuzhiyun * picks the end of ram, wherever that may be. The location of the stack, 57*4882a593Smuzhiyun * the relocation address, and how far U-Boot is moved by relocation are 58*4882a593Smuzhiyun * set in the global data structure. 59*4882a593Smuzhiyun */ board_get_usable_ram_top(ulong total_size)60*4882a593Smuzhiyunulong board_get_usable_ram_top(ulong total_size) 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun return fsp_get_usable_lowmem_top(gd->arch.hob_list); 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun install_e820_map(unsigned max_entries,struct e820entry * entries)65*4882a593Smuzhiyununsigned install_e820_map(unsigned max_entries, struct e820entry *entries) 66*4882a593Smuzhiyun { 67*4882a593Smuzhiyun unsigned num_entries = 0; 68*4882a593Smuzhiyun const struct hob_header *hdr; 69*4882a593Smuzhiyun struct hob_res_desc *res_desc; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun hdr = gd->arch.hob_list; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun while (!end_of_hob(hdr)) { 74*4882a593Smuzhiyun if (hdr->type == HOB_TYPE_RES_DESC) { 75*4882a593Smuzhiyun res_desc = (struct hob_res_desc *)hdr; 76*4882a593Smuzhiyun entries[num_entries].addr = res_desc->phys_start; 77*4882a593Smuzhiyun entries[num_entries].size = res_desc->len; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun if (res_desc->type == RES_SYS_MEM) 80*4882a593Smuzhiyun entries[num_entries].type = E820_RAM; 81*4882a593Smuzhiyun else if (res_desc->type == RES_MEM_RESERVED) 82*4882a593Smuzhiyun entries[num_entries].type = E820_RESERVED; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun num_entries++; 85*4882a593Smuzhiyun } 86*4882a593Smuzhiyun hdr = get_next_hob(hdr); 87*4882a593Smuzhiyun } 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Mark PCIe ECAM address range as reserved */ 90*4882a593Smuzhiyun entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; 91*4882a593Smuzhiyun entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; 92*4882a593Smuzhiyun entries[num_entries].type = E820_RESERVED; 93*4882a593Smuzhiyun num_entries++; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #ifdef CONFIG_HAVE_ACPI_RESUME 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * Everything between U-Boot's stack and ram top needs to be 98*4882a593Smuzhiyun * reserved in order for ACPI S3 resume to work. 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; 101*4882a593Smuzhiyun entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \ 102*4882a593Smuzhiyun CONFIG_STACK_SIZE; 103*4882a593Smuzhiyun entries[num_entries].type = E820_RESERVED; 104*4882a593Smuzhiyun num_entries++; 105*4882a593Smuzhiyun #endif 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun return num_entries; 108*4882a593Smuzhiyun } 109