1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * This library provides CMOS (inside RTC SRAM) access routines at a very 9*4882a593Smuzhiyun * early stage when driver model is not available yet. Only read access is 10*4882a593Smuzhiyun * provided. The 16-bit/32-bit read are compatible with driver model RTC 11*4882a593Smuzhiyun * uclass write ops, that data is stored in little-endian mode. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <common.h> 15*4882a593Smuzhiyun #include <asm/early_cmos.h> 16*4882a593Smuzhiyun #include <asm/io.h> 17*4882a593Smuzhiyun cmos_read8(u8 addr)18*4882a593Smuzhiyunu8 cmos_read8(u8 addr) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun outb(addr, CMOS_IO_PORT); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun return inb(CMOS_IO_PORT + 1); 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun cmos_read16(u8 addr)25*4882a593Smuzhiyunu16 cmos_read16(u8 addr) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun u16 value = 0; 28*4882a593Smuzhiyun u16 data; 29*4882a593Smuzhiyun int i; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun for (i = 0; i < sizeof(value); i++) { 32*4882a593Smuzhiyun data = cmos_read8(addr + i); 33*4882a593Smuzhiyun value |= data << (i << 3); 34*4882a593Smuzhiyun } 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun return value; 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun cmos_read32(u8 addr)39*4882a593Smuzhiyunu32 cmos_read32(u8 addr) 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun u32 value = 0; 42*4882a593Smuzhiyun u32 data; 43*4882a593Smuzhiyun int i; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun for (i = 0; i < sizeof(value); i++) { 46*4882a593Smuzhiyun data = cmos_read8(addr + i); 47*4882a593Smuzhiyun value |= data << (i << 3); 48*4882a593Smuzhiyun } 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun return value; 51*4882a593Smuzhiyun } 52