1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/e820.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Install a default e820 table with 4 entries as follows: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * 0x000000-0x0a0000 Useable RAM 16*4882a593Smuzhiyun * 0x0a0000-0x100000 Reserved for ISA 17*4882a593Smuzhiyun * 0x100000-gd->ram_size Useable RAM 18*4882a593Smuzhiyun * CONFIG_PCIE_ECAM_BASE PCIe ECAM 19*4882a593Smuzhiyun */ install_e820_map(unsigned max_entries,struct e820entry * entries)20*4882a593Smuzhiyun__weak unsigned install_e820_map(unsigned max_entries, 21*4882a593Smuzhiyun struct e820entry *entries) 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun entries[0].addr = 0; 24*4882a593Smuzhiyun entries[0].size = ISA_START_ADDRESS; 25*4882a593Smuzhiyun entries[0].type = E820_RAM; 26*4882a593Smuzhiyun entries[1].addr = ISA_START_ADDRESS; 27*4882a593Smuzhiyun entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; 28*4882a593Smuzhiyun entries[1].type = E820_RESERVED; 29*4882a593Smuzhiyun entries[2].addr = ISA_END_ADDRESS; 30*4882a593Smuzhiyun entries[2].size = gd->ram_size - ISA_END_ADDRESS; 31*4882a593Smuzhiyun entries[2].type = E820_RAM; 32*4882a593Smuzhiyun entries[3].addr = CONFIG_PCIE_ECAM_BASE; 33*4882a593Smuzhiyun entries[3].size = CONFIG_PCIE_ECAM_SIZE; 34*4882a593Smuzhiyun entries[3].type = E820_RESERVED; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun return 4; 37*4882a593Smuzhiyun } 38