1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/msr.h>
9*4882a593Smuzhiyun #include <asm/mtrr.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
12*4882a593Smuzhiyun "Uncacheable",
13*4882a593Smuzhiyun "Combine",
14*4882a593Smuzhiyun "2",
15*4882a593Smuzhiyun "3",
16*4882a593Smuzhiyun "Through",
17*4882a593Smuzhiyun "Protect",
18*4882a593Smuzhiyun "Back",
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
do_mtrr_list(void)21*4882a593Smuzhiyun static int do_mtrr_list(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun int i;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
26*4882a593Smuzhiyun "Mask ||", "Size ||");
27*4882a593Smuzhiyun for (i = 0; i < MTRR_COUNT; i++) {
28*4882a593Smuzhiyun const char *type = "Invalid";
29*4882a593Smuzhiyun uint64_t base, mask, size;
30*4882a593Smuzhiyun bool valid;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
33*4882a593Smuzhiyun mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
34*4882a593Smuzhiyun size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
35*4882a593Smuzhiyun size |= (1 << 12) - 1;
36*4882a593Smuzhiyun size += 1;
37*4882a593Smuzhiyun valid = mask & MTRR_PHYS_MASK_VALID;
38*4882a593Smuzhiyun type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
39*4882a593Smuzhiyun printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
40*4882a593Smuzhiyun valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
41*4882a593Smuzhiyun mask & ~MTRR_PHYS_MASK_VALID, size);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
do_mtrr_set(uint reg,int argc,char * const argv[])47*4882a593Smuzhiyun static int do_mtrr_set(uint reg, int argc, char * const argv[])
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun const char *typename = argv[0];
50*4882a593Smuzhiyun struct mtrr_state state;
51*4882a593Smuzhiyun uint32_t start, size;
52*4882a593Smuzhiyun uint64_t base, mask;
53*4882a593Smuzhiyun int i, type = -1;
54*4882a593Smuzhiyun bool valid;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (argc < 3)
57*4882a593Smuzhiyun return CMD_RET_USAGE;
58*4882a593Smuzhiyun for (i = 0; i < MTRR_TYPE_COUNT; i++) {
59*4882a593Smuzhiyun if (*typename == *mtrr_type_name[i])
60*4882a593Smuzhiyun type = i;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun if (type == -1) {
63*4882a593Smuzhiyun printf("Invalid type name %s\n", typename);
64*4882a593Smuzhiyun return CMD_RET_USAGE;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun start = simple_strtoul(argv[1], NULL, 16);
67*4882a593Smuzhiyun size = simple_strtoul(argv[2], NULL, 16);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun base = start | type;
70*4882a593Smuzhiyun valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
71*4882a593Smuzhiyun mask = ~((uint64_t)size - 1);
72*4882a593Smuzhiyun mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
73*4882a593Smuzhiyun if (valid)
74*4882a593Smuzhiyun mask |= MTRR_PHYS_MASK_VALID;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun printf("base=%llx, mask=%llx\n", base, mask);
77*4882a593Smuzhiyun mtrr_open(&state);
78*4882a593Smuzhiyun wrmsrl(MTRR_PHYS_BASE_MSR(reg), base);
79*4882a593Smuzhiyun wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
80*4882a593Smuzhiyun mtrr_close(&state);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
mtrr_set_valid(int reg,bool valid)85*4882a593Smuzhiyun static int mtrr_set_valid(int reg, bool valid)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct mtrr_state state;
88*4882a593Smuzhiyun uint64_t mask;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun mtrr_open(&state);
91*4882a593Smuzhiyun mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg));
92*4882a593Smuzhiyun if (valid)
93*4882a593Smuzhiyun mask |= MTRR_PHYS_MASK_VALID;
94*4882a593Smuzhiyun else
95*4882a593Smuzhiyun mask &= ~MTRR_PHYS_MASK_VALID;
96*4882a593Smuzhiyun wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
97*4882a593Smuzhiyun mtrr_close(&state);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
do_mtrr(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])102*4882a593Smuzhiyun static int do_mtrr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun const char *cmd;
105*4882a593Smuzhiyun uint reg;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun cmd = argv[1];
108*4882a593Smuzhiyun if (argc < 2 || *cmd == 'l')
109*4882a593Smuzhiyun return do_mtrr_list();
110*4882a593Smuzhiyun argc -= 2;
111*4882a593Smuzhiyun argv += 2;
112*4882a593Smuzhiyun if (argc <= 0)
113*4882a593Smuzhiyun return CMD_RET_USAGE;
114*4882a593Smuzhiyun reg = simple_strtoul(argv[0], NULL, 16);
115*4882a593Smuzhiyun if (reg >= MTRR_COUNT) {
116*4882a593Smuzhiyun printf("Invalid register number\n");
117*4882a593Smuzhiyun return CMD_RET_USAGE;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun if (*cmd == 'e')
120*4882a593Smuzhiyun return mtrr_set_valid(reg, true);
121*4882a593Smuzhiyun else if (*cmd == 'd')
122*4882a593Smuzhiyun return mtrr_set_valid(reg, false);
123*4882a593Smuzhiyun else if (*cmd == 's')
124*4882a593Smuzhiyun return do_mtrr_set(reg, argc - 1, argv + 1);
125*4882a593Smuzhiyun else
126*4882a593Smuzhiyun return CMD_RET_USAGE;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return 0;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun U_BOOT_CMD(
132*4882a593Smuzhiyun mtrr, 6, 1, do_mtrr,
133*4882a593Smuzhiyun "Use x86 memory type range registers (32-bit only)",
134*4882a593Smuzhiyun "[list] - list current registers\n"
135*4882a593Smuzhiyun "set <reg> <type> <start> <size> - set a register\n"
136*4882a593Smuzhiyun "\t<type> is Uncacheable, Combine, Through, Protect, Back\n"
137*4882a593Smuzhiyun "disable <reg> - disable a register\n"
138*4882a593Smuzhiyun "ensable <reg> - enable a register"
139*4882a593Smuzhiyun );
140