1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2002
3*4882a593Smuzhiyun * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _U_BOOT_I386_H_
9*4882a593Smuzhiyun #define _U_BOOT_I386_H_ 1
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct global_data;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun extern char gdt_rom[];
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* cpu/.../cpu.c */
16*4882a593Smuzhiyun int arch_cpu_init(void);
17*4882a593Smuzhiyun int x86_cpu_init_f(void);
18*4882a593Smuzhiyun int cpu_init_f(void);
19*4882a593Smuzhiyun void setup_gdt(struct global_data *id, u64 *gdt_addr);
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Setup FSP execution environment GDT to use the one we used in
22*4882a593Smuzhiyun * arch/x86/cpu/start16.S and reload the segment registers.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun void setup_fsp_gdt(void);
25*4882a593Smuzhiyun int init_cache(void);
26*4882a593Smuzhiyun int cleanup_before_linux(void);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* cpu/.../timer.c */
29*4882a593Smuzhiyun void timer_isr(void *);
30*4882a593Smuzhiyun typedef void (timer_fnc_t) (void);
31*4882a593Smuzhiyun int register_timer_isr (timer_fnc_t *isr_func);
32*4882a593Smuzhiyun unsigned long get_tbclk_mhz(void);
33*4882a593Smuzhiyun void timer_set_base(uint64_t base);
34*4882a593Smuzhiyun int i8254_init(void);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* cpu/.../interrupts.c */
37*4882a593Smuzhiyun int cpu_init_interrupts(void);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun int cleanup_before_linux(void);
40*4882a593Smuzhiyun int x86_cleanup_before_linux(void);
41*4882a593Smuzhiyun void x86_enable_caches(void);
42*4882a593Smuzhiyun void x86_disable_caches(void);
43*4882a593Smuzhiyun int x86_init_cache(void);
44*4882a593Smuzhiyun void reset_cpu(ulong addr);
45*4882a593Smuzhiyun ulong board_get_usable_ram_top(ulong total_size);
46*4882a593Smuzhiyun int default_print_cpuinfo(void);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Set up a UART which can be used with printch(), printhex8(), etc. */
49*4882a593Smuzhiyun int setup_internal_uart(int enable);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun void setup_pcat_compatibility(void);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun void isa_unmap_rom(u32 addr);
54*4882a593Smuzhiyun u32 isa_map_rom(u32 bus_addr, int size);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* arch/x86/lib/... */
57*4882a593Smuzhiyun int video_bios_init(void);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* arch/x86/lib/fsp/... */
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /**
62*4882a593Smuzhiyun * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * At the end of pre-relocation phase, save the new stack address
65*4882a593Smuzhiyun * to CMOS and use it as the stack on next S3 boot for fsp_init()
66*4882a593Smuzhiyun * continuation function.
67*4882a593Smuzhiyun *
68*4882a593Smuzhiyun * @return: 0 if OK, -ve on error
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun int fsp_save_s3_stack(void);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
73*4882a593Smuzhiyun void board_init_f_r(void) __attribute__ ((noreturn));
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun int arch_misc_init(void);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Read the time stamp counter */
rdtsc(void)78*4882a593Smuzhiyun static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun uint32_t high, low;
81*4882a593Smuzhiyun __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
82*4882a593Smuzhiyun return (((uint64_t)high) << 32) | low;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* board/... */
86*4882a593Smuzhiyun void timer_set_tsc_base(uint64_t new_base);
87*4882a593Smuzhiyun uint64_t timer_get_tsc(void);
88*4882a593Smuzhiyun void board_quiesce_devices(void);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun void quick_ram_check(void);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define PCI_VGA_RAM_IMAGE_START 0xc0000
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #endif /* _U_BOOT_I386_H_ */
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