1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * From Coreboot file of same name 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007-2009 coresystems GmbH 5*4882a593Smuzhiyun * 2012 secunet Security Networks AG 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASM_SPEEDSTEP_H 11*4882a593Smuzhiyun #define _ASM_SPEEDSTEP_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Magic value used to locate speedstep configuration in the device tree */ 14*4882a593Smuzhiyun #define SPEEDSTEP_APIC_MAGIC 0xACAC 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* MWAIT coordination I/O base address. This must match 17*4882a593Smuzhiyun * the \_PR_.CPU0 PM base address. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define PMB0_BASE 0x510 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* PMB1: I/O port that triggers SMI once cores are in the same state. 22*4882a593Smuzhiyun * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define PMB1_BASE 0x800 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct sst_state { 27*4882a593Smuzhiyun uint8_t dynfsb:1; /* whether this is SLFM */ 28*4882a593Smuzhiyun uint8_t nonint:1; /* add .5 to ratio */ 29*4882a593Smuzhiyun uint8_t ratio:6; 30*4882a593Smuzhiyun uint8_t vid; 31*4882a593Smuzhiyun uint8_t is_turbo; 32*4882a593Smuzhiyun uint8_t is_slfm; 33*4882a593Smuzhiyun uint32_t power; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun #define SPEEDSTEP_RATIO_SHIFT 8 36*4882a593Smuzhiyun #define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) 37*4882a593Smuzhiyun #define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) 38*4882a593Smuzhiyun #define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) 39*4882a593Smuzhiyun #define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) 40*4882a593Smuzhiyun #define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) 41*4882a593Smuzhiyun #define SPEEDSTEP_VID_MASK 0x3f 42*4882a593Smuzhiyun #define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ 43*4882a593Smuzhiyun 0, /* dynfsb won't be read. */ \ 44*4882a593Smuzhiyun ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ 45*4882a593Smuzhiyun (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ 46*4882a593Smuzhiyun >> SPEEDSTEP_RATIO_SHIFT), \ 47*4882a593Smuzhiyun (val & mask) & SPEEDSTEP_VID_MASK, \ 48*4882a593Smuzhiyun 0, /* not turbo by default */ \ 49*4882a593Smuzhiyun 0, /* not slfm by default */ \ 50*4882a593Smuzhiyun 0 /* power is hardcoded in software. */ \ 51*4882a593Smuzhiyun }) 52*4882a593Smuzhiyun #define SPEEDSTEP_ENCODE_STATE(state) ( \ 53*4882a593Smuzhiyun ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ 54*4882a593Smuzhiyun ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ 55*4882a593Smuzhiyun ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ 56*4882a593Smuzhiyun ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) 57*4882a593Smuzhiyun #define SPEEDSTEP_DOUBLE_RATIO(state) ( \ 58*4882a593Smuzhiyun ((uint8_t)(state).ratio * 2) + (state).nonint) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct sst_params { 61*4882a593Smuzhiyun struct sst_state slfm; 62*4882a593Smuzhiyun struct sst_state min; 63*4882a593Smuzhiyun struct sst_state max; 64*4882a593Smuzhiyun struct sst_state turbo; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Looking at core2's spec, the highest normal bus ratio for an eist enabled 68*4882a593Smuzhiyun processor is 14, the lowest is always 6. This makes 5 states with the 69*4882a593Smuzhiyun minimal step width of 2. With turbo mode and super LFM we have at most 7. */ 70*4882a593Smuzhiyun #define SPEEDSTEP_MAX_NORMAL_STATES 5 71*4882a593Smuzhiyun #define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) 72*4882a593Smuzhiyun struct sst_table { 73*4882a593Smuzhiyun /* Table of p-states for EMTTM and ACPI by decreasing performance. */ 74*4882a593Smuzhiyun struct sst_state states[SPEEDSTEP_MAX_STATES]; 75*4882a593Smuzhiyun int num_states; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun void speedstep_gen_pstates(struct sst_table *); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define SPEEDSTEP_MAX_POWER_YONAH 31000 81*4882a593Smuzhiyun #define SPEEDSTEP_MIN_POWER_YONAH 13100 82*4882a593Smuzhiyun #define SPEEDSTEP_MAX_POWER_MEROM 35000 83*4882a593Smuzhiyun #define SPEEDSTEP_MIN_POWER_MEROM 25000 84*4882a593Smuzhiyun #define SPEEDSTEP_SLFM_POWER_MEROM 12000 85*4882a593Smuzhiyun #define SPEEDSTEP_MAX_POWER_PENRYN 35000 86*4882a593Smuzhiyun #define SPEEDSTEP_MIN_POWER_PENRYN 15000 87*4882a593Smuzhiyun #define SPEEDSTEP_SLFM_POWER_PENRYN 12000 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif 90