1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_PROCESSOR_H_ 9*4882a593Smuzhiyun #define __ASM_PROCESSOR_H_ 1 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define X86_GDT_ENTRY_SIZE 8 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define X86_GDT_ENTRY_NULL 0 14*4882a593Smuzhiyun #define X86_GDT_ENTRY_UNUSED 1 15*4882a593Smuzhiyun #define X86_GDT_ENTRY_32BIT_CS 2 16*4882a593Smuzhiyun #define X86_GDT_ENTRY_32BIT_DS 3 17*4882a593Smuzhiyun #define X86_GDT_ENTRY_32BIT_FS 4 18*4882a593Smuzhiyun #define X86_GDT_ENTRY_16BIT_CS 5 19*4882a593Smuzhiyun #define X86_GDT_ENTRY_16BIT_DS 6 20*4882a593Smuzhiyun #define X86_GDT_ENTRY_16BIT_FLAT_CS 7 21*4882a593Smuzhiyun #define X86_GDT_ENTRY_16BIT_FLAT_DS 8 22*4882a593Smuzhiyun #define X86_GDT_NUM_ENTRIES 9 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Length of the public header on Intel microcode blobs */ 27*4882a593Smuzhiyun #define UCODE_HEADER_LEN 0x30 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * This register is documented in (for example) the Intel Atom Processor E3800 33*4882a593Smuzhiyun * Product Family Datasheet in "PCU - Power Management Controller (PMC)". 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * RST_CNT: Reset Control Register (RST_CNT) Offset cf9. 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * The naming follows Intel's naming. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define IO_PORT_RESET 0xcf9 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun enum { 42*4882a593Smuzhiyun SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ 43*4882a593Smuzhiyun RST_CPU = 1 << 2, /* initiate reset */ 44*4882a593Smuzhiyun FULL_RST = 1 << 3, /* full power cycle */ 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /** 48*4882a593Smuzhiyun * x86_full_reset() - reset everything: perform a full power cycle 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun void x86_full_reset(void); 51*4882a593Smuzhiyun cpu_hlt(void)52*4882a593Smuzhiyunstatic inline __attribute__((always_inline)) void cpu_hlt(void) 53*4882a593Smuzhiyun { 54*4882a593Smuzhiyun asm("hlt"); 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun cpu_get_sp(void)57*4882a593Smuzhiyunstatic inline ulong cpu_get_sp(void) 58*4882a593Smuzhiyun { 59*4882a593Smuzhiyun ulong result; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun asm volatile( 62*4882a593Smuzhiyun "mov %%esp, %%eax" 63*4882a593Smuzhiyun : "=a" (result)); 64*4882a593Smuzhiyun return result; 65*4882a593Smuzhiyun } 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70