1*4882a593Smuzhiyun #ifndef _ASM_X86_PROCESSOR_FLAGS_H 2*4882a593Smuzhiyun #define _ASM_X86_PROCESSOR_FLAGS_H 3*4882a593Smuzhiyun /* Various flags defined: can be included from assembler. */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * EFLAGS bits 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 9*4882a593Smuzhiyun #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 10*4882a593Smuzhiyun #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ 11*4882a593Smuzhiyun #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 12*4882a593Smuzhiyun #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 13*4882a593Smuzhiyun #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 14*4882a593Smuzhiyun #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 15*4882a593Smuzhiyun #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 16*4882a593Smuzhiyun #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 17*4882a593Smuzhiyun #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 18*4882a593Smuzhiyun #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 19*4882a593Smuzhiyun #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 20*4882a593Smuzhiyun #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 21*4882a593Smuzhiyun #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 22*4882a593Smuzhiyun #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 23*4882a593Smuzhiyun #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 24*4882a593Smuzhiyun #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Basic CPU control in CR0 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define X86_CR0_PE 0x00000001 /* Protection Enable */ 30*4882a593Smuzhiyun #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ 31*4882a593Smuzhiyun #define X86_CR0_EM 0x00000004 /* Emulation */ 32*4882a593Smuzhiyun #define X86_CR0_TS 0x00000008 /* Task Switched */ 33*4882a593Smuzhiyun #define X86_CR0_ET 0x00000010 /* Extension Type */ 34*4882a593Smuzhiyun #define X86_CR0_NE 0x00000020 /* Numeric Error */ 35*4882a593Smuzhiyun #define X86_CR0_WP 0x00010000 /* Write Protect */ 36*4882a593Smuzhiyun #define X86_CR0_AM 0x00040000 /* Alignment Mask */ 37*4882a593Smuzhiyun #define X86_CR0_NW 0x20000000 /* Not Write-through */ 38*4882a593Smuzhiyun #define X86_CR0_CD 0x40000000 /* Cache Disable */ 39*4882a593Smuzhiyun #define X86_CR0_PG 0x80000000 /* Paging */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Paging options in CR3 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define X86_CR3_PWT 0x00000008 /* Page Write Through */ 45*4882a593Smuzhiyun #define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * Intel CPU features in CR4 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ 51*4882a593Smuzhiyun #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ 52*4882a593Smuzhiyun #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ 53*4882a593Smuzhiyun #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ 54*4882a593Smuzhiyun #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ 55*4882a593Smuzhiyun #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ 56*4882a593Smuzhiyun #define X86_CR4_MCE 0x00000040 /* Machine check enable */ 57*4882a593Smuzhiyun #define X86_CR4_PGE 0x00000080 /* enable global pages */ 58*4882a593Smuzhiyun #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ 59*4882a593Smuzhiyun #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 60*4882a593Smuzhiyun #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 61*4882a593Smuzhiyun #define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ 62*4882a593Smuzhiyun #define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * x86-64 Task Priority Register, CR8 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun #define X86_CR8_TPR 0x0000000F /* task priority register */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * NSC/Cyrix CPU configuration register indexes 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define CX86_PCR0 0x20 77*4882a593Smuzhiyun #define CX86_GCR 0xb8 78*4882a593Smuzhiyun #define CX86_CCR0 0xc0 79*4882a593Smuzhiyun #define CX86_CCR1 0xc1 80*4882a593Smuzhiyun #define CX86_CCR2 0xc2 81*4882a593Smuzhiyun #define CX86_CCR3 0xc3 82*4882a593Smuzhiyun #define CX86_CCR4 0xe8 83*4882a593Smuzhiyun #define CX86_CCR5 0xe9 84*4882a593Smuzhiyun #define CX86_CCR6 0xea 85*4882a593Smuzhiyun #define CX86_CCR7 0xeb 86*4882a593Smuzhiyun #define CX86_PCR1 0xf0 87*4882a593Smuzhiyun #define CX86_DIR0 0xfe 88*4882a593Smuzhiyun #define CX86_DIR1 0xff 89*4882a593Smuzhiyun #define CX86_ARR_BASE 0xc4 90*4882a593Smuzhiyun #define CX86_RCR_BASE 0xdc 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #ifdef __KERNEL__ 93*4882a593Smuzhiyun #ifdef CONFIG_VM86 94*4882a593Smuzhiyun #define X86_VM_MASK X86_EFLAGS_VM 95*4882a593Smuzhiyun #else 96*4882a593Smuzhiyun #define X86_VM_MASK 0 /* No VM86 support */ 97*4882a593Smuzhiyun #endif 98*4882a593Smuzhiyun #endif 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #endif /* _ASM_X86_PROCESSOR_FLAGS_H */ 101