1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __asm_pch_common_h 8*4882a593Smuzhiyun #define __asm_pch_common_h 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Common Intel SATA registers */ 11*4882a593Smuzhiyun #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ 12*4882a593Smuzhiyun #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ 13*4882a593Smuzhiyun #define SATA_SP 0xd0 /* Scratchpad */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define INTR_LN 0x3c 16*4882a593Smuzhiyun #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ 17*4882a593Smuzhiyun #define IDE_DECODE_ENABLE (1 << 15) 18*4882a593Smuzhiyun #define IDE_SITRE (1 << 14) 19*4882a593Smuzhiyun #define IDE_ISP_5_CLOCKS (0 << 12) 20*4882a593Smuzhiyun #define IDE_ISP_4_CLOCKS (1 << 12) 21*4882a593Smuzhiyun #define IDE_ISP_3_CLOCKS (2 << 12) 22*4882a593Smuzhiyun #define IDE_RCT_4_CLOCKS (0 << 8) 23*4882a593Smuzhiyun #define IDE_RCT_3_CLOCKS (1 << 8) 24*4882a593Smuzhiyun #define IDE_RCT_2_CLOCKS (2 << 8) 25*4882a593Smuzhiyun #define IDE_RCT_1_CLOCKS (3 << 8) 26*4882a593Smuzhiyun #define IDE_DTE1 (1 << 7) 27*4882a593Smuzhiyun #define IDE_PPE1 (1 << 6) 28*4882a593Smuzhiyun #define IDE_IE1 (1 << 5) 29*4882a593Smuzhiyun #define IDE_TIME1 (1 << 4) 30*4882a593Smuzhiyun #define IDE_DTE0 (1 << 3) 31*4882a593Smuzhiyun #define IDE_PPE0 (1 << 2) 32*4882a593Smuzhiyun #define IDE_IE0 (1 << 1) 33*4882a593Smuzhiyun #define IDE_TIME0 (1 << 0) 34*4882a593Smuzhiyun #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define SERIRQ_CNTL 0x64 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /** 39*4882a593Smuzhiyun * pch_common_sir_read() - Read from a SATA indexed register 40*4882a593Smuzhiyun * 41*4882a593Smuzhiyun * @dev: SATA device 42*4882a593Smuzhiyun * @idx: Register index to read 43*4882a593Smuzhiyun * @return value read from register 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun u32 pch_common_sir_read(struct udevice *dev, int idx); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /** 48*4882a593Smuzhiyun * pch_common_sir_write() - Write to a SATA indexed register 49*4882a593Smuzhiyun * 50*4882a593Smuzhiyun * @dev: SATA device 51*4882a593Smuzhiyun * @idx: Register index to write 52*4882a593Smuzhiyun * @value: Value to write 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun void pch_common_sir_write(struct udevice *dev, int idx, u32 value); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif 57