1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ARCH_IRQ_H_ 8*4882a593Smuzhiyun #define _ARCH_IRQ_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <dt-bindings/interrupt-router/intel-irq.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * Intel interrupt router configuration mechanism 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * There are two known ways of Intel interrupt router configuration mechanism 16*4882a593Smuzhiyun * so far. On most cases, the IRQ routing configuraiton is controlled by PCI 17*4882a593Smuzhiyun * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). 18*4882a593Smuzhiyun * On some newer platforms like BayTrail and Braswell, the IRQ routing is now 19*4882a593Smuzhiyun * in the IBASE register block where IBASE is memory-mapped. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun enum pirq_config { 22*4882a593Smuzhiyun PIRQ_VIA_PCI, 23*4882a593Smuzhiyun PIRQ_VIA_IBASE 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /** 27*4882a593Smuzhiyun * Intel interrupt router control block 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * Its members' value will be filled in based on device tree's input. 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE 32*4882a593Smuzhiyun * @link_base: link value base number 33*4882a593Smuzhiyun * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means 34*4882a593Smuzhiyun * IRQ N is available to be routed 35*4882a593Smuzhiyun * @lb_bdf: irq router's PCI bus/device/function number encoding 36*4882a593Smuzhiyun * @ibase: IBASE register block base address 37*4882a593Smuzhiyun * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset) 38*4882a593Smuzhiyun * @actl_addr: ACTL register offset 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun struct irq_router { 41*4882a593Smuzhiyun int config; 42*4882a593Smuzhiyun u32 link_base; 43*4882a593Smuzhiyun u16 irq_mask; 44*4882a593Smuzhiyun u32 bdf; 45*4882a593Smuzhiyun u32 ibase; 46*4882a593Smuzhiyun bool actl_8bit; 47*4882a593Smuzhiyun int actl_addr; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct pirq_routing { 51*4882a593Smuzhiyun int bdf; 52*4882a593Smuzhiyun int pin; 53*4882a593Smuzhiyun int pirq; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* PIRQ link number and value conversion */ 57*4882a593Smuzhiyun #define LINK_V2N(link, base) (link - base) 58*4882a593Smuzhiyun #define LINK_N2V(link, base) (link + base) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define PIRQ_BITMAP 0xdef8 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /** 63*4882a593Smuzhiyun * irq_router_common_init() - Perform common x86 interrupt init 64*4882a593Smuzhiyun * 65*4882a593Smuzhiyun * This creates the PIRQ routing table and routes the IRQs 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun int irq_router_common_init(struct udevice *dev); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* _ARCH_IRQ_H_ */ 70