1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* i8259.h i8259 PIC Registers */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASMI386_I8259_H_ 11*4882a593Smuzhiyun #define _ASMI386_I8959_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* PIC I/O mapped registers */ 14*4882a593Smuzhiyun #define IRR 0x0 /* Interrupt Request Register */ 15*4882a593Smuzhiyun #define ISR 0x0 /* In-Service Register */ 16*4882a593Smuzhiyun #define ICW1 0x0 /* Initialization Control Word 1 */ 17*4882a593Smuzhiyun #define OCW2 0x0 /* Operation Control Word 2 */ 18*4882a593Smuzhiyun #define OCW3 0x0 /* Operation Control Word 3 */ 19*4882a593Smuzhiyun #define ICW2 0x1 /* Initialization Control Word 2 */ 20*4882a593Smuzhiyun #define ICW3 0x1 /* Initialization Control Word 3 */ 21*4882a593Smuzhiyun #define ICW4 0x1 /* Initialization Control Word 4 */ 22*4882a593Smuzhiyun #define IMR 0x1 /* Interrupt Mask Register */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* IRR, IMR, ISR and ICW3 bits */ 25*4882a593Smuzhiyun #define IR7 0x80 /* IR7 */ 26*4882a593Smuzhiyun #define IR6 0x40 /* IR6 */ 27*4882a593Smuzhiyun #define IR5 0x20 /* IR5 */ 28*4882a593Smuzhiyun #define IR4 0x10 /* IR4 */ 29*4882a593Smuzhiyun #define IR3 0x08 /* IR3 */ 30*4882a593Smuzhiyun #define IR2 0x04 /* IR2 */ 31*4882a593Smuzhiyun #define IR1 0x02 /* IR1 */ 32*4882a593Smuzhiyun #define IR0 0x01 /* IR0 */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* SEOI bits */ 35*4882a593Smuzhiyun #define SEOI_IR7 0x07 /* IR7 */ 36*4882a593Smuzhiyun #define SEOI_IR6 0x06 /* IR6 */ 37*4882a593Smuzhiyun #define SEOI_IR5 0x05 /* IR5 */ 38*4882a593Smuzhiyun #define SEOI_IR4 0x04 /* IR4 */ 39*4882a593Smuzhiyun #define SEOI_IR3 0x03 /* IR3 */ 40*4882a593Smuzhiyun #define SEOI_IR2 0x02 /* IR2 */ 41*4882a593Smuzhiyun #define SEOI_IR1 0x01 /* IR1 */ 42*4882a593Smuzhiyun #define SEOI_IR0 0x00 /* IR0 */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* OCW2 bits */ 45*4882a593Smuzhiyun #define OCW2_RCLR 0x00 /* Rotate/clear */ 46*4882a593Smuzhiyun #define OCW2_NEOI 0x20 /* Non specific EOI */ 47*4882a593Smuzhiyun #define OCW2_NOP 0x40 /* NOP */ 48*4882a593Smuzhiyun #define OCW2_SEOI 0x60 /* Specific EOI */ 49*4882a593Smuzhiyun #define OCW2_RSET 0x80 /* Rotate/set */ 50*4882a593Smuzhiyun #define OCW2_REOI 0xa0 /* Rotate on non specific EOI */ 51*4882a593Smuzhiyun #define OCW2_PSET 0xc0 /* Priority Set Command */ 52*4882a593Smuzhiyun #define OCW2_RSEOI 0xe0 /* Rotate on specific EOI */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* ICW1 bits */ 55*4882a593Smuzhiyun #define ICW1_SEL 0x10 /* Select ICW1 */ 56*4882a593Smuzhiyun #define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */ 57*4882a593Smuzhiyun #define ICW1_ADI 0x04 /* Address Interval */ 58*4882a593Smuzhiyun #define ICW1_SNGL 0x02 /* Single PIC */ 59*4882a593Smuzhiyun #define ICW1_EICW4 0x01 /* Expect initilization ICW4 */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * ICW2 is the starting vector number 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * ICW2 is bit-mask of present slaves for a master device, 65*4882a593Smuzhiyun * or the slave ID for a slave device 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* ICW4 bits */ 69*4882a593Smuzhiyun #define ICW4_AEOI 0x02 /* Automatic EOI Mode */ 70*4882a593Smuzhiyun #define ICW4_PM 0x01 /* Microprocessor Mode */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define ELCR1 0x4d0 73*4882a593Smuzhiyun #define ELCR2 0x4d1 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun int i8259_init(void); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif /* _ASMI386_I8959_H_ */ 78