1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002-2010 3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_GBL_DATA_H 9*4882a593Smuzhiyun #define __ASM_GBL_DATA_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/processor.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum pei_boot_mode_t { 16*4882a593Smuzhiyun PEI_BOOT_NONE = 0, 17*4882a593Smuzhiyun PEI_BOOT_SOFT_RESET, 18*4882a593Smuzhiyun PEI_BOOT_RESUME, 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct dimm_info { 23*4882a593Smuzhiyun uint32_t dimm_size; 24*4882a593Smuzhiyun uint16_t ddr_type; 25*4882a593Smuzhiyun uint16_t ddr_frequency; 26*4882a593Smuzhiyun uint8_t rank_per_dimm; 27*4882a593Smuzhiyun uint8_t channel_num; 28*4882a593Smuzhiyun uint8_t dimm_num; 29*4882a593Smuzhiyun uint8_t bank_locator; 30*4882a593Smuzhiyun /* The 5th byte is '\0' for the end of string */ 31*4882a593Smuzhiyun uint8_t serial[5]; 32*4882a593Smuzhiyun /* The 19th byte is '\0' for the end of string */ 33*4882a593Smuzhiyun uint8_t module_part_number[19]; 34*4882a593Smuzhiyun uint16_t mod_id; 35*4882a593Smuzhiyun uint8_t mod_type; 36*4882a593Smuzhiyun uint8_t bus_width; 37*4882a593Smuzhiyun } __packed; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct pei_memory_info { 40*4882a593Smuzhiyun uint8_t dimm_cnt; 41*4882a593Smuzhiyun /* Maximum num of dimm is 8 */ 42*4882a593Smuzhiyun struct dimm_info dimm[8]; 43*4882a593Smuzhiyun } __packed; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct memory_area { 46*4882a593Smuzhiyun uint64_t start; 47*4882a593Smuzhiyun uint64_t size; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct memory_info { 51*4882a593Smuzhiyun int num_areas; 52*4882a593Smuzhiyun uint64_t total_memory; 53*4882a593Smuzhiyun uint64_t total_32bit_memory; 54*4882a593Smuzhiyun struct memory_area area[CONFIG_NR_DRAM_BANKS]; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MAX_MTRR_REQUESTS 8 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /** 60*4882a593Smuzhiyun * A request for a memory region to be set up in a particular way. These 61*4882a593Smuzhiyun * requests are processed before board_init_r() is called. They are generally 62*4882a593Smuzhiyun * optional and can be ignored with some performance impact. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun struct mtrr_request { 65*4882a593Smuzhiyun int type; /* MTRR_TYPE_... */ 66*4882a593Smuzhiyun uint64_t start; 67*4882a593Smuzhiyun uint64_t size; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Architecture-specific global data */ 71*4882a593Smuzhiyun struct arch_global_data { 72*4882a593Smuzhiyun u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16); 73*4882a593Smuzhiyun struct global_data *gd_addr; /* Location of Global Data */ 74*4882a593Smuzhiyun uint8_t x86; /* CPU family */ 75*4882a593Smuzhiyun uint8_t x86_vendor; /* CPU vendor */ 76*4882a593Smuzhiyun uint8_t x86_model; 77*4882a593Smuzhiyun uint8_t x86_mask; 78*4882a593Smuzhiyun uint32_t x86_device; 79*4882a593Smuzhiyun uint64_t tsc_base; /* Initial value returned by rdtsc() */ 80*4882a593Smuzhiyun void *new_fdt; /* Relocated FDT */ 81*4882a593Smuzhiyun uint32_t bist; /* Built-in self test value */ 82*4882a593Smuzhiyun enum pei_boot_mode_t pei_boot_mode; 83*4882a593Smuzhiyun const struct pch_gpio_map *gpio_map; /* board GPIO map */ 84*4882a593Smuzhiyun struct memory_info meminfo; /* Memory information */ 85*4882a593Smuzhiyun struct pei_memory_info pei_meminfo; /* PEI memory information */ 86*4882a593Smuzhiyun #ifdef CONFIG_HAVE_FSP 87*4882a593Smuzhiyun void *hob_list; /* FSP HOB list */ 88*4882a593Smuzhiyun #endif 89*4882a593Smuzhiyun struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS]; 90*4882a593Smuzhiyun int mtrr_req_count; 91*4882a593Smuzhiyun int has_mtrr; 92*4882a593Smuzhiyun /* MRC training data to save for the next boot */ 93*4882a593Smuzhiyun char *mrc_output; 94*4882a593Smuzhiyun unsigned int mrc_output_len; 95*4882a593Smuzhiyun ulong table; /* Table pointer from previous loader */ 96*4882a593Smuzhiyun int turbo_state; /* Current turbo state */ 97*4882a593Smuzhiyun struct irq_routing_table *pirq_routing_table; 98*4882a593Smuzhiyun #ifdef CONFIG_SEABIOS 99*4882a593Smuzhiyun u32 high_table_ptr; 100*4882a593Smuzhiyun u32 high_table_limit; 101*4882a593Smuzhiyun #endif 102*4882a593Smuzhiyun #ifdef CONFIG_HAVE_ACPI_RESUME 103*4882a593Smuzhiyun int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */ 104*4882a593Smuzhiyun ulong backup_mem; /* Backup memory address for S3 */ 105*4882a593Smuzhiyun #endif 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #include <asm-generic/global_data.h> 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 113*4882a593Smuzhiyun # if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */ 116*4882a593Smuzhiyun #define gd global_data_ptr 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr 119*4882a593Smuzhiyun # else get_fs_gd_ptr(void)120*4882a593Smuzhiyunstatic inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void) 121*4882a593Smuzhiyun { 122*4882a593Smuzhiyun gd_t *gd_ptr; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(X86_64) 125*4882a593Smuzhiyun asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr)); 126*4882a593Smuzhiyun #else 127*4882a593Smuzhiyun asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr)); 128*4882a593Smuzhiyun #endif 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun return gd_ptr; 131*4882a593Smuzhiyun } 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define gd get_fs_gd_ptr() 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define DECLARE_GLOBAL_DATA_PTR 136*4882a593Smuzhiyun # endif 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #endif 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* 141*4882a593Smuzhiyun * Our private Global Data Flags 142*4882a593Smuzhiyun */ 143*4882a593Smuzhiyun #define GD_FLG_COLD_BOOT 0x10000 /* Cold Boot */ 144*4882a593Smuzhiyun #define GD_FLG_WARM_BOOT 0x20000 /* Warm Boot */ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* __ASM_GBL_DATA_H */ 147