1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_CPU_COMMON_H 8*4882a593Smuzhiyun #define __ASM_CPU_COMMON_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define IA32_PERF_CTL 0x199 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /** 13*4882a593Smuzhiyun * cpu_common_init() - Set up common CPU init 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * This reports BIST failure, enables the LAPIC, updates microcode, enables 16*4882a593Smuzhiyun * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * @return 0 if OK, -ve on error 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun int cpu_common_init(void); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /** 23*4882a593Smuzhiyun * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * If a change is needed, this function will do a soft reset so it takes 26*4882a593Smuzhiyun * effect. 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * Some details are available here: 29*4882a593Smuzhiyun * http://forum.hwbot.org/showthread.php?t=76092 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * @return 0 if OK, -ve on error 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun int cpu_set_flex_ratio_to_tdp_nominal(void); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36