1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CMOS_LAYOUT_H 8*4882a593Smuzhiyun #define __CMOS_LAYOUT_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * The RTC internal registers and RAM is organized as two banks of 128 bytes 12*4882a593Smuzhiyun * each, called the standard and extended banks. The first 14 bytes of the 13*4882a593Smuzhiyun * standard bank contain the RTC time and date information along with four 14*4882a593Smuzhiyun * registers, A - D, that are used for configuration of the RTC. The extended 15*4882a593Smuzhiyun * bank contains a full 128 bytes of battery backed SRAM. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * For simplicity in U-Boot we only support CMOS in the standard bank, and 18*4882a593Smuzhiyun * its base address starts from offset 0x10, which leaves us 112 bytes space. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CMOS_BASE 0x10 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * The file records all offsets off CMOS_BASE that is currently used by 24*4882a593Smuzhiyun * U-Boot for various reasons. It is put in such a unified place in order 25*4882a593Smuzhiyun * to be consistent across platforms. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* stack address for S3 boot in a FSP configuration, 4 bytes */ 29*4882a593Smuzhiyun #define CMOS_FSP_STACK_ADDR CMOS_BASE 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif /* __CMOS_LAYOUT_H */ 32