1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __X86_CACHE_H__ 8*4882a593Smuzhiyun #define __X86_CACHE_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise 12*4882a593Smuzhiyun * use 64-bytes, a safe default for x86. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifndef CONFIG_SYS_CACHELINE_SIZE 15*4882a593Smuzhiyun #define CONFIG_SYS_CACHELINE_SIZE 64 16*4882a593Smuzhiyun #endif 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 19*4882a593Smuzhiyun wbinvd(void)20*4882a593Smuzhiyunstatic inline void wbinvd(void) 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun asm volatile ("wbinvd" : : : "memory"); 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun invd(void)25*4882a593Smuzhiyunstatic inline void invd(void) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun asm volatile("invd" : : : "memory"); 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Enable caches and write buffer */ 31*4882a593Smuzhiyun void enable_caches(void); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Disable caches and write buffer */ 34*4882a593Smuzhiyun void disable_caches(void); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __X86_CACHE_H__ */ 37