1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _X86_ARCH_TNC_H_ 8*4882a593Smuzhiyun #define _X86_ARCH_TNC_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* IGD Function Disable Register */ 11*4882a593Smuzhiyun #define IGD_FD 0xc4 12*4882a593Smuzhiyun #define FUNC_DISABLE 0x00000001 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Memory BAR Enable */ 15*4882a593Smuzhiyun #define MEM_BAR_EN 0x00000001 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* LPC PCI Configuration Registers */ 18*4882a593Smuzhiyun #define LPC_RCBA 0xf0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Root Complex Register Block */ 21*4882a593Smuzhiyun struct tnc_rcba { 22*4882a593Smuzhiyun u32 rctl; 23*4882a593Smuzhiyun u32 esd; 24*4882a593Smuzhiyun u32 rsvd1[2]; 25*4882a593Smuzhiyun u32 hdd; 26*4882a593Smuzhiyun u32 rsvd2; 27*4882a593Smuzhiyun u32 hdba; 28*4882a593Smuzhiyun u32 rsvd3[3129]; 29*4882a593Smuzhiyun u32 d31ip; 30*4882a593Smuzhiyun u32 rsvd4[3]; 31*4882a593Smuzhiyun u32 d27ip; 32*4882a593Smuzhiyun u32 rsvd5; 33*4882a593Smuzhiyun u32 d02ip; 34*4882a593Smuzhiyun u32 rsvd6; 35*4882a593Smuzhiyun u32 d26ip; 36*4882a593Smuzhiyun u32 d25ip; 37*4882a593Smuzhiyun u32 d24ip; 38*4882a593Smuzhiyun u32 d23ip; 39*4882a593Smuzhiyun u32 d03ip; 40*4882a593Smuzhiyun u32 rsvd7[3]; 41*4882a593Smuzhiyun u16 d31ir; 42*4882a593Smuzhiyun u16 rsvd8[3]; 43*4882a593Smuzhiyun u16 d27ir; 44*4882a593Smuzhiyun u16 d26ir; 45*4882a593Smuzhiyun u16 d25ir; 46*4882a593Smuzhiyun u16 d24ir; 47*4882a593Smuzhiyun u16 d23ir; 48*4882a593Smuzhiyun u16 rsvd9[7]; 49*4882a593Smuzhiyun u16 d02ir; 50*4882a593Smuzhiyun u16 d03ir; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif /* _X86_ARCH_TNC_H_ */ 54