1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _QUARK_DEVICE_H_ 8*4882a593Smuzhiyun #define _QUARK_DEVICE_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Internal PCI device numbers within the SoC. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Note it must start with 0x_ prefix, as the device number macro will be 14*4882a593Smuzhiyun * included in the ACPI ASL files (see irq_helper.h and irq_route.h). 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define QUARK_HOST_BRIDGE_DEV 0x00 18*4882a593Smuzhiyun #define QUARK_HOST_BRIDGE_FUNC 0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define QUARK_DEV_20 0x14 21*4882a593Smuzhiyun #define QUARK_MMC_SDIO_FUNC 0 22*4882a593Smuzhiyun #define QUARK_UART0_FUNC 1 23*4882a593Smuzhiyun #define QUARK_USB_DEVICE_FUNC 2 24*4882a593Smuzhiyun #define QUARK_USB_EHCI_FUNC 3 25*4882a593Smuzhiyun #define QUARK_USB_OHCI_FUNC 4 26*4882a593Smuzhiyun #define QUARK_UART1_FUNC 5 27*4882a593Smuzhiyun #define QUARK_EMAC0_FUNC 6 28*4882a593Smuzhiyun #define QUARK_EMAC1_FUNC 7 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define QUARK_DEV_21 0x15 31*4882a593Smuzhiyun #define QUARK_SPI0_FUNC 0 32*4882a593Smuzhiyun #define QUARK_SPI1_FUNC 1 33*4882a593Smuzhiyun #define QUARK_I2C_GPIO_FUNC 2 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define QUARK_DEV_23 0x17 36*4882a593Smuzhiyun #define QUARK_PCIE0_FUNC 0 37*4882a593Smuzhiyun #define QUARK_PCIE1_FUNC 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define QUARK_LGC_BRIDGE_DEV 0x1f 40*4882a593Smuzhiyun #define QUARK_LGC_BRIDGE_FUNC 0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 43*4882a593Smuzhiyun #include <pci.h> 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define QUARK_HOST_BRIDGE \ 46*4882a593Smuzhiyun PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC) 47*4882a593Smuzhiyun #define QUARK_MMC_SDIO \ 48*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC) 49*4882a593Smuzhiyun #define QUARK_UART0 \ 50*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC) 51*4882a593Smuzhiyun #define QUARK_USB_DEVICE \ 52*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC) 53*4882a593Smuzhiyun #define QUARK_USB_EHCI \ 54*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC) 55*4882a593Smuzhiyun #define QUARK_USB_OHCI \ 56*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC) 57*4882a593Smuzhiyun #define QUARK_UART1 \ 58*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC) 59*4882a593Smuzhiyun #define QUARK_EMAC0 \ 60*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC) 61*4882a593Smuzhiyun #define QUARK_EMAC1 \ 62*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC) 63*4882a593Smuzhiyun #define QUARK_SPI0 \ 64*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC) 65*4882a593Smuzhiyun #define QUARK_SPI1 \ 66*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC) 67*4882a593Smuzhiyun #define QUARK_I2C_GPIO \ 68*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC) 69*4882a593Smuzhiyun #define QUARK_PCIE0 \ 70*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC) 71*4882a593Smuzhiyun #define QUARK_PCIE1 \ 72*4882a593Smuzhiyun PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC) 73*4882a593Smuzhiyun #define QUARK_LEGACY_BRIDGE \ 74*4882a593Smuzhiyun PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC) 75*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif /* _QUARK_DEVICE_H_ */ 78