1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2014 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * From Coreboot file of the same name 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2007-2008 coresystems GmbH 7*4882a593Smuzhiyun * Copyright (C) 2011 Google Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _ACH_ASM_SANDYBRIDGE_H 13*4882a593Smuzhiyun #define _ACH_ASM_SANDYBRIDGE_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Chipset types */ 16*4882a593Smuzhiyun #define SANDYBRIDGE_MOBILE 0 17*4882a593Smuzhiyun #define SANDYBRIDGE_DESKTOP 1 18*4882a593Smuzhiyun #define SANDYBRIDGE_SERVER 2 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Device ID for SandyBridge and IvyBridge */ 21*4882a593Smuzhiyun #define BASE_REV_SNB 0x00 22*4882a593Smuzhiyun #define BASE_REV_IVB 0x50 23*4882a593Smuzhiyun #define BASE_REV_MASK 0x50 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* SandyBridge CPU stepping */ 26*4882a593Smuzhiyun #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ 27*4882a593Smuzhiyun #define SNB_STEP_D1 (BASE_REV_SNB + 6) 28*4882a593Smuzhiyun #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* IvyBridge CPU stepping */ 31*4882a593Smuzhiyun #define IVB_STEP_A0 (BASE_REV_IVB + 0) 32*4882a593Smuzhiyun #define IVB_STEP_B0 (BASE_REV_IVB + 2) 33*4882a593Smuzhiyun #define IVB_STEP_C0 (BASE_REV_IVB + 4) 34*4882a593Smuzhiyun #define IVB_STEP_K0 (BASE_REV_IVB + 5) 35*4882a593Smuzhiyun #define IVB_STEP_D0 (BASE_REV_IVB + 6) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Intel Enhanced Debug region must be 4MB */ 38*4882a593Smuzhiyun #define IED_SIZE 0x400000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Northbridge BARs */ 41*4882a593Smuzhiyun #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ 42*4882a593Smuzhiyun #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ 43*4882a593Smuzhiyun #define DEFAULT_RCBABASE 0xfed1c000 44*4882a593Smuzhiyun /* 4 KB per PCIe device */ 45*4882a593Smuzhiyun #define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Device 0:0.0 PCI configuration space (Host Bridge) */ 48*4882a593Smuzhiyun #define EPBAR 0x40 49*4882a593Smuzhiyun #define MCHBAR 0x48 50*4882a593Smuzhiyun #define PCIEXBAR 0x60 51*4882a593Smuzhiyun #define DMIBAR 0x68 52*4882a593Smuzhiyun #define X60BAR 0x60 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define GGC 0x50 /* GMCH Graphics Control */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define DEVEN 0x54 /* Device Enable */ 57*4882a593Smuzhiyun #define DEVEN_PEG60 (1 << 13) 58*4882a593Smuzhiyun #define DEVEN_IGD (1 << 4) 59*4882a593Smuzhiyun #define DEVEN_PEG10 (1 << 3) 60*4882a593Smuzhiyun #define DEVEN_PEG11 (1 << 2) 61*4882a593Smuzhiyun #define DEVEN_PEG12 (1 << 1) 62*4882a593Smuzhiyun #define DEVEN_HOST (1 << 0) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PAM0 0x80 65*4882a593Smuzhiyun #define PAM1 0x81 66*4882a593Smuzhiyun #define PAM2 0x82 67*4882a593Smuzhiyun #define PAM3 0x83 68*4882a593Smuzhiyun #define PAM4 0x84 69*4882a593Smuzhiyun #define PAM5 0x85 70*4882a593Smuzhiyun #define PAM6 0x86 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define LAC 0x87 /* Legacy Access Control */ 73*4882a593Smuzhiyun #define SMRAM 0x88 /* System Management RAM Control */ 74*4882a593Smuzhiyun #define D_OPEN (1 << 6) 75*4882a593Smuzhiyun #define D_CLS (1 << 5) 76*4882a593Smuzhiyun #define D_LCK (1 << 4) 77*4882a593Smuzhiyun #define G_SMRAME (1 << 3) 78*4882a593Smuzhiyun #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define TOM 0xa0 81*4882a593Smuzhiyun #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ 82*4882a593Smuzhiyun #define TSEG 0xb8 /* TSEG base */ 83*4882a593Smuzhiyun #define TOLUD 0xbc /* Top of Low Used Memory */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define SKPAD 0xdc /* Scratchpad Data */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Device 0:1.0 PCI configuration space (PCI Express) */ 88*4882a593Smuzhiyun #define BCTRL1 0x3e /* 16bit */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Device 0:2.0 PCI configuration space (Graphics Device) */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define MSAC 0x62 /* Multi Size Aperture Control */ 93*4882a593Smuzhiyun #define SWSCI 0xe8 /* SWSCI enable */ 94*4882a593Smuzhiyun #define ASLS 0xfc /* OpRegion Base */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * MCHBAR 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun #define SSKPD 0x5d14 /* 16bit (scratchpad) */ 100*4882a593Smuzhiyun #define BIOS_RESET_CPL 0x5da8 /* 8bit */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * DMIBAR 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /** 109*4882a593Smuzhiyun * bridge_silicon_revision() - Get the Northbridge revision 110*4882a593Smuzhiyun * 111*4882a593Smuzhiyun * @dev: Northbridge device 112*4882a593Smuzhiyun * @return revision ID (bits 3:0) and bridge ID (bits 7:4) 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun int bridge_silicon_revision(struct udevice *dev); 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif 117