1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011, Google Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef ASM_ARCH_PEI_DATA_H 8*4882a593Smuzhiyun #define ASM_ARCH_PEI_DATA_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/linkage.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct pch_usb3_controller_settings { 13*4882a593Smuzhiyun /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ 14*4882a593Smuzhiyun uint16_t mode; 15*4882a593Smuzhiyun /* 4 bit mask, 1: switchable, 0: not switchable */ 16*4882a593Smuzhiyun uint16_t hs_port_switch_mask; 17*4882a593Smuzhiyun /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ 18*4882a593Smuzhiyun uint16_t preboot_support; 19*4882a593Smuzhiyun /* 0: Disable, 1: Enable */ 20*4882a593Smuzhiyun uint16_t xhci_streams; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun typedef asmlinkage void (*tx_byte_func)(unsigned char byte); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PEI_VERSION 6 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct __packed pei_data { 28*4882a593Smuzhiyun uint32_t pei_version; 29*4882a593Smuzhiyun uint32_t mchbar; 30*4882a593Smuzhiyun uint32_t dmibar; 31*4882a593Smuzhiyun uint32_t epbar; 32*4882a593Smuzhiyun uint32_t pciexbar; 33*4882a593Smuzhiyun uint16_t smbusbar; 34*4882a593Smuzhiyun uint32_t wdbbar; 35*4882a593Smuzhiyun uint32_t wdbsize; 36*4882a593Smuzhiyun uint32_t hpet_address; 37*4882a593Smuzhiyun uint32_t rcba; 38*4882a593Smuzhiyun uint32_t pmbase; 39*4882a593Smuzhiyun uint32_t gpiobase; 40*4882a593Smuzhiyun uint32_t thermalbase; 41*4882a593Smuzhiyun uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ 42*4882a593Smuzhiyun uint32_t tseg_size; 43*4882a593Smuzhiyun uint8_t spd_addresses[4]; 44*4882a593Smuzhiyun uint8_t ts_addresses[4]; 45*4882a593Smuzhiyun int boot_mode; 46*4882a593Smuzhiyun int ec_present; 47*4882a593Smuzhiyun int gbe_enable; 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * 0 = leave channel enabled 50*4882a593Smuzhiyun * 1 = disable dimm 0 on channel 51*4882a593Smuzhiyun * 2 = disable dimm 1 on channel 52*4882a593Smuzhiyun * 3 = disable dimm 0+1 on channel 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun int dimm_channel0_disabled; 55*4882a593Smuzhiyun int dimm_channel1_disabled; 56*4882a593Smuzhiyun /* Seed values saved in CMOS */ 57*4882a593Smuzhiyun uint32_t scrambler_seed; 58*4882a593Smuzhiyun uint32_t scrambler_seed_s3; 59*4882a593Smuzhiyun /* Data read from flash and passed into MRC */ 60*4882a593Smuzhiyun unsigned char *mrc_input; 61*4882a593Smuzhiyun unsigned int mrc_input_len; 62*4882a593Smuzhiyun /* Data from MRC that should be saved to flash */ 63*4882a593Smuzhiyun unsigned char *mrc_output; 64*4882a593Smuzhiyun unsigned int mrc_output_len; 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * Max frequency DDR3 could be ran at. Could be one of four values: 67*4882a593Smuzhiyun * 800, 1067, 1333, 1600 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun uint32_t max_ddr3_freq; 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * USB Port Configuration: 72*4882a593Smuzhiyun * [0] = enable 73*4882a593Smuzhiyun * [1] = overcurrent pin 74*4882a593Smuzhiyun * [2] = length 75*4882a593Smuzhiyun * 76*4882a593Smuzhiyun * Ports 0-7 can be mapped to OC0-OC3 77*4882a593Smuzhiyun * Ports 8-13 can be mapped to OC4-OC7 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * Port Length 80*4882a593Smuzhiyun * MOBILE: 81*4882a593Smuzhiyun * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) 82*4882a593Smuzhiyun * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) 83*4882a593Smuzhiyun * DESKTOP: 84*4882a593Smuzhiyun * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) 85*4882a593Smuzhiyun * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) 86*4882a593Smuzhiyun * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun uint16_t usb_port_config[16][3]; 89*4882a593Smuzhiyun /* See the usb3 struct above for details */ 90*4882a593Smuzhiyun struct pch_usb3_controller_settings usb3; 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * SPD data array for onboard RAM. Specify address 0xf0, 93*4882a593Smuzhiyun * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in 94*4882a593Smuzhiyun * spd_address for a given "DIMM". 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun uint8_t spd_data[4][256]; 97*4882a593Smuzhiyun tx_byte_func tx_byte; 98*4882a593Smuzhiyun int ddr3lv_support; 99*4882a593Smuzhiyun /* 100*4882a593Smuzhiyun * pcie_init needs to be set to 1 to have the system agent initialise 101*4882a593Smuzhiyun * PCIe. Note: This should only be required if your system has Gen3 102*4882a593Smuzhiyun * devices and it will increase your boot time by at least 100ms. 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun int pcie_init; 105*4882a593Smuzhiyun /* 106*4882a593Smuzhiyun * N mode functionality. Leave this setting at 0. 107*4882a593Smuzhiyun * 0 Auto 108*4882a593Smuzhiyun * 1 1N 109*4882a593Smuzhiyun * 2 2N 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun int nmode; 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows 114*4882a593Smuzhiyun * for DIMM SPD data to specify whether double-rate is required for 115*4882a593Smuzhiyun * extended operating temperature range. 116*4882a593Smuzhiyun * 0 Enable double rate based upon temperature thresholds 117*4882a593Smuzhiyun * 1 Normal rate 118*4882a593Smuzhiyun * 2 Always enable double rate 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun int ddr_refresh_rate_config; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif 124