1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * From Coreboot file of the same name 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 The ChromiumOS Authors. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_ARCH_MODEL_206AX_H 10*4882a593Smuzhiyun #define _ASM_ARCH_MODEL_206AX_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ 13*4882a593Smuzhiyun #define SANDYBRIDGE_BCLK 100 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CPUID_VMX (1 << 5) 16*4882a593Smuzhiyun #define CPUID_SMX (1 << 6) 17*4882a593Smuzhiyun #define MSR_FEATURE_CONFIG 0x13c 18*4882a593Smuzhiyun #define IA32_PLATFORM_DCA_CAP 0x1f8 19*4882a593Smuzhiyun #define IA32_MISC_ENABLE 0x1a0 20*4882a593Smuzhiyun #define MSR_TEMPERATURE_TARGET 0x1a2 21*4882a593Smuzhiyun #define IA32_THERM_INTERRUPT 0x19b 22*4882a593Smuzhiyun #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 23*4882a593Smuzhiyun #define ENERGY_POLICY_PERFORMANCE 0 24*4882a593Smuzhiyun #define ENERGY_POLICY_NORMAL 6 25*4882a593Smuzhiyun #define ENERGY_POLICY_POWERSAVE 15 26*4882a593Smuzhiyun #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 27*4882a593Smuzhiyun #define MSR_LT_LOCK_MEMORY 0x2e7 28*4882a593Smuzhiyun #define IA32_MC0_STATUS 0x401 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define MSR_MISC_PWR_MGMT 0x1aa 31*4882a593Smuzhiyun #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define MSR_PKGC3_IRTL 0x60a 34*4882a593Smuzhiyun #define MSR_PKGC6_IRTL 0x60b 35*4882a593Smuzhiyun #define MSR_PKGC7_IRTL 0x60c 36*4882a593Smuzhiyun #define IRTL_VALID (1 << 15) 37*4882a593Smuzhiyun #define IRTL_1_NS (0 << 10) 38*4882a593Smuzhiyun #define IRTL_32_NS (1 << 10) 39*4882a593Smuzhiyun #define IRTL_1024_NS (2 << 10) 40*4882a593Smuzhiyun #define IRTL_32768_NS (3 << 10) 41*4882a593Smuzhiyun #define IRTL_1048576_NS (4 << 10) 42*4882a593Smuzhiyun #define IRTL_33554432_NS (5 << 10) 43*4882a593Smuzhiyun #define IRTL_RESPONSE_MASK (0x3ff) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MSR_PP0_CURRENT_CONFIG 0x601 46*4882a593Smuzhiyun #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ 47*4882a593Smuzhiyun #define MSR_PP1_CURRENT_CONFIG 0x602 48*4882a593Smuzhiyun #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ 49*4882a593Smuzhiyun #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ 50*4882a593Smuzhiyun #define MSR_PKG_POWER_SKU 0x614 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 53*4882a593Smuzhiyun #define MSR_CONFIG_TDP_LEVEL1 0x649 54*4882a593Smuzhiyun #define MSR_CONFIG_TDP_LEVEL2 0x64a 55*4882a593Smuzhiyun #define MSR_CONFIG_TDP_CONTROL 0x64b 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* P-state configuration */ 58*4882a593Smuzhiyun #define PSS_MAX_ENTRIES 8 59*4882a593Smuzhiyun #define PSS_RATIO_STEP 2 60*4882a593Smuzhiyun #define PSS_LATENCY_TRANSITION 10 61*4882a593Smuzhiyun #define PSS_LATENCY_BUSMASTER 10 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Configure power limits for turbo mode */ 64*4882a593Smuzhiyun void set_power_limits(u8 power_limit_1_time); 65*4882a593Smuzhiyun int cpu_config_tdp_levels(void); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68