1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Google Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is from coreboot soc/intel/broadwell/include/soc/spi.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _BROADWELL_SPI_H_ 10*4882a593Smuzhiyun #define _BROADWELL_SPI_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * SPI Opcode Menu setup for SPIBAR lockdown 14*4882a593Smuzhiyun * should support most common flash chips. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SPIBAR_OFFSET 0x3800 18*4882a593Smuzhiyun #define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x))) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Reigsters within the SPIBAR */ 21*4882a593Smuzhiyun #define SPIBAR_SSFC 0x91 22*4882a593Smuzhiyun #define SPIBAR_FDOC 0xb0 23*4882a593Smuzhiyun #define SPIBAR_FDOD 0xb4 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define SPIBAR_PREOP 0x94 26*4882a593Smuzhiyun #define SPIBAR_OPTYPE 0x96 27*4882a593Smuzhiyun #define SPIBAR_OPMENU_LOWER 0x98 28*4882a593Smuzhiyun #define SPIBAR_OPMENU_UPPER 0x9c 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ 31*4882a593Smuzhiyun #define SPI_OPTYPE_0 0x01 /* Write, no address */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ 34*4882a593Smuzhiyun #define SPI_OPTYPE_1 0x03 /* Write, address required */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define SPI_OPMENU_2 0x03 /* READ: Read Data */ 37*4882a593Smuzhiyun #define SPI_OPTYPE_2 0x02 /* Read, address required */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ 40*4882a593Smuzhiyun #define SPI_OPTYPE_3 0x00 /* Read, no address */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ 43*4882a593Smuzhiyun #define SPI_OPTYPE_4 0x03 /* Write, address required */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ 46*4882a593Smuzhiyun #define SPI_OPTYPE_5 0x00 /* Read, no address */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ 49*4882a593Smuzhiyun #define SPI_OPTYPE_6 0x03 /* Write, address required */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ 52*4882a593Smuzhiyun #define SPI_OPTYPE_7 0x02 /* Read, address required */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ 55*4882a593Smuzhiyun (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) 56*4882a593Smuzhiyun #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ 57*4882a593Smuzhiyun (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ 60*4882a593Smuzhiyun (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ 61*4882a593Smuzhiyun (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ 62*4882a593Smuzhiyun (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ 67*4882a593Smuzhiyun #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ 68*4882a593Smuzhiyun #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ 69*4882a593Smuzhiyun #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ 70*4882a593Smuzhiyun #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ 71*4882a593Smuzhiyun #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ 72*4882a593Smuzhiyun #define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */ 73*4882a593Smuzhiyun #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) 74*4882a593Smuzhiyun #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ 75*4882a593Smuzhiyun #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ 76*4882a593Smuzhiyun #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ 77*4882a593Smuzhiyun #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ 78*4882a593Smuzhiyun #define SPIBAR_FADDR 0x08 /* SPI flash address */ 79*4882a593Smuzhiyun #define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */ 80*4882a593Smuzhiyun #define SPIBAR_SSFS 0x90 81*4882a593Smuzhiyun #define SPIBAR_SSFS_ERROR (1 << 3) 82*4882a593Smuzhiyun #define SPIBAR_SSFS_DONE (1 << 2) 83*4882a593Smuzhiyun #define SPIBAR_SSFC 0x91 84*4882a593Smuzhiyun #define SPIBAR_SSFC_DATA (1 << 14) 85*4882a593Smuzhiyun #define SPIBAR_SSFC_GO (1 << 1) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif 88