1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __asm_arch_rcba_h 8*4882a593Smuzhiyun #define __asm_arch_rcba_h 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define PMSYNC_CONFIG 0x33c4 /* 32bit */ 11*4882a593Smuzhiyun #define PMSYNC_CONFIG2 0x33cc /* 32bit */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define DEEP_S3_POL 0x3328 /* 32bit */ 14*4882a593Smuzhiyun #define DEEP_S3_EN_AC (1 << 0) 15*4882a593Smuzhiyun #define DEEP_S3_EN_DC (1 << 1) 16*4882a593Smuzhiyun #define DEEP_S5_POL 0x3330 /* 32bit */ 17*4882a593Smuzhiyun #define DEEP_S5_EN_AC (1 << 14) 18*4882a593Smuzhiyun #define DEEP_S5_EN_DC (1 << 15) 19*4882a593Smuzhiyun #define DEEP_SX_CONFIG 0x3334 /* 32bit */ 20*4882a593Smuzhiyun #define DEEP_SX_WAKE_PIN_EN (1 << 2) 21*4882a593Smuzhiyun #define DEEP_SX_ACPRESENT_PD (1 << 1) 22*4882a593Smuzhiyun #define DEEP_SX_GP27_PIN_EN (1 << 0) 23*4882a593Smuzhiyun #define PMSYNC_CONFIG 0x33c4 /* 32bit */ 24*4882a593Smuzhiyun #define PMSYNC_CONFIG2 0x33cc /* 32bit */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define RC 0x3400 /* 32bit */ 27*4882a593Smuzhiyun #define HPTC 0x3404 /* 32bit */ 28*4882a593Smuzhiyun #define GCS 0x3410 /* 32bit */ 29*4882a593Smuzhiyun #define BUC 0x3414 /* 32bit */ 30*4882a593Smuzhiyun #define PCH_DISABLE_GBE (1 << 5) 31*4882a593Smuzhiyun #define FD 0x3418 /* 32bit */ 32*4882a593Smuzhiyun #define FDSW 0x3420 /* 8bit */ 33*4882a593Smuzhiyun #define DISPBDF 0x3424 /* 16bit */ 34*4882a593Smuzhiyun #define FD2 0x3428 /* 32bit */ 35*4882a593Smuzhiyun #define CG 0x341c /* 32bit */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Function Disable 1 RCBA 0x3418 */ 38*4882a593Smuzhiyun #define PCH_DISABLE_ALWAYS (1 << 0) 39*4882a593Smuzhiyun #define PCH_DISABLE_ADSPD (1 << 1) 40*4882a593Smuzhiyun #define PCH_DISABLE_SATA1 (1 << 2) 41*4882a593Smuzhiyun #define PCH_DISABLE_SMBUS (1 << 3) 42*4882a593Smuzhiyun #define PCH_DISABLE_HD_AUDIO (1 << 4) 43*4882a593Smuzhiyun #define PCH_DISABLE_EHCI2 (1 << 13) 44*4882a593Smuzhiyun #define PCH_DISABLE_LPC (1 << 14) 45*4882a593Smuzhiyun #define PCH_DISABLE_EHCI1 (1 << 15) 46*4882a593Smuzhiyun #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) 47*4882a593Smuzhiyun #define PCH_DISABLE_THERMAL (1 << 24) 48*4882a593Smuzhiyun #define PCH_DISABLE_SATA2 (1 << 25) 49*4882a593Smuzhiyun #define PCH_DISABLE_XHCI (1 << 27) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Function Disable 2 RCBA 0x3428 */ 52*4882a593Smuzhiyun #define PCH_DISABLE_KT (1 << 4) 53*4882a593Smuzhiyun #define PCH_DISABLE_IDER (1 << 3) 54*4882a593Smuzhiyun #define PCH_DISABLE_MEI2 (1 << 2) 55*4882a593Smuzhiyun #define PCH_DISABLE_MEI1 (1 << 1) 56*4882a593Smuzhiyun #define PCH_ENABLE_DBDF (1 << 0) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif 59