1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * From coreboot src/soc/intel/broadwell/include/soc/pm.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 Google, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_PM_H 10*4882a593Smuzhiyun #define __ASM_ARCH_PM_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define PM1_STS 0x00 13*4882a593Smuzhiyun #define WAK_STS (1 << 15) 14*4882a593Smuzhiyun #define PCIEXPWAK_STS (1 << 14) 15*4882a593Smuzhiyun #define PRBTNOR_STS (1 << 11) 16*4882a593Smuzhiyun #define RTC_STS (1 << 10) 17*4882a593Smuzhiyun #define PWRBTN_STS (1 << 8) 18*4882a593Smuzhiyun #define GBL_STS (1 << 5) 19*4882a593Smuzhiyun #define BM_STS (1 << 4) 20*4882a593Smuzhiyun #define TMROF_STS (1 << 0) 21*4882a593Smuzhiyun #define PM1_EN 0x02 22*4882a593Smuzhiyun #define PCIEXPWAK_DIS (1 << 14) 23*4882a593Smuzhiyun #define RTC_EN (1 << 10) 24*4882a593Smuzhiyun #define PWRBTN_EN (1 << 8) 25*4882a593Smuzhiyun #define GBL_EN (1 << 5) 26*4882a593Smuzhiyun #define TMROF_EN (1 << 0) 27*4882a593Smuzhiyun #define PM1_CNT 0x04 28*4882a593Smuzhiyun #define SLP_EN (1 << 13) 29*4882a593Smuzhiyun #define SLP_TYP (7 << 10) 30*4882a593Smuzhiyun #define SLP_TYP_SHIFT 10 31*4882a593Smuzhiyun #define SLP_TYP_S0 0 32*4882a593Smuzhiyun #define SLP_TYP_S1 1 33*4882a593Smuzhiyun #define SLP_TYP_S3 5 34*4882a593Smuzhiyun #define SLP_TYP_S4 6 35*4882a593Smuzhiyun #define SLP_TYP_S5 7 36*4882a593Smuzhiyun #define GBL_RLS (1 << 2) 37*4882a593Smuzhiyun #define BM_RLD (1 << 1) 38*4882a593Smuzhiyun #define SCI_EN (1 << 0) 39*4882a593Smuzhiyun #define PM1_TMR 0x08 40*4882a593Smuzhiyun #define SMI_EN 0x30 41*4882a593Smuzhiyun #define XHCI_SMI_EN (1 << 31) 42*4882a593Smuzhiyun #define ME_SMI_EN (1 << 30) 43*4882a593Smuzhiyun #define GPIO_UNLOCK_SMI_EN (1 << 27) 44*4882a593Smuzhiyun #define INTEL_USB2_EN (1 << 18) 45*4882a593Smuzhiyun #define LEGACY_USB2_EN (1 << 17) 46*4882a593Smuzhiyun #define PERIODIC_EN (1 << 14) 47*4882a593Smuzhiyun #define TCO_EN (1 << 13) 48*4882a593Smuzhiyun #define MCSMI_EN (1 << 11) 49*4882a593Smuzhiyun #define BIOS_RLS (1 << 7) 50*4882a593Smuzhiyun #define SWSMI_TMR_EN (1 << 6) 51*4882a593Smuzhiyun #define APMC_EN (1 << 5) 52*4882a593Smuzhiyun #define SLP_SMI_EN (1 << 4) 53*4882a593Smuzhiyun #define LEGACY_USB_EN (1 << 3) 54*4882a593Smuzhiyun #define BIOS_EN (1 << 2) 55*4882a593Smuzhiyun #define EOS (1 << 1) 56*4882a593Smuzhiyun #define GBL_SMI_EN (1 << 0) 57*4882a593Smuzhiyun #define SMI_STS 0x34 58*4882a593Smuzhiyun #define UPWRC 0x3c 59*4882a593Smuzhiyun #define UPWRC_WS (1 << 8) 60*4882a593Smuzhiyun #define UPWRC_WE (1 << 1) 61*4882a593Smuzhiyun #define UPWRC_SMI (1 << 0) 62*4882a593Smuzhiyun #define GPE_CNTL 0x42 63*4882a593Smuzhiyun #define SWGPE_CTRL (1 << 1) 64*4882a593Smuzhiyun #define DEVACT_STS 0x44 65*4882a593Smuzhiyun #define PM2_CNT 0x50 66*4882a593Smuzhiyun #define TCO1_CNT 0x60 67*4882a593Smuzhiyun #define TCO_TMR_HLT (1 << 11) 68*4882a593Smuzhiyun #define TCO1_STS 0x64 69*4882a593Smuzhiyun #define DMISCI_STS (1 << 9) 70*4882a593Smuzhiyun #define TCO2_STS 0x66 71*4882a593Smuzhiyun #define TCO2_STS_SECOND_TO (1 << 1) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define GPE0_REG_MAX 4 74*4882a593Smuzhiyun #define GPE0_REG_SIZE 32 75*4882a593Smuzhiyun #define GPE0_STS(x) (0x80 + (x * 4)) 76*4882a593Smuzhiyun #define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */ 77*4882a593Smuzhiyun #define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */ 78*4882a593Smuzhiyun #define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */ 79*4882a593Smuzhiyun #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ 80*4882a593Smuzhiyun #define WADT_STS (1 << 18) 81*4882a593Smuzhiyun #define GP27_STS (1 << 16) 82*4882a593Smuzhiyun #define PME_B0_STS (1 << 13) 83*4882a593Smuzhiyun #define ME_SCI_STS (1 << 12) 84*4882a593Smuzhiyun #define PME_STS (1 << 11) 85*4882a593Smuzhiyun #define BATLOW_STS (1 << 10) 86*4882a593Smuzhiyun #define PCI_EXP_STS (1 << 9) 87*4882a593Smuzhiyun #define SMB_WAK_STS (1 << 7) 88*4882a593Smuzhiyun #define TCOSCI_STS (1 << 6) 89*4882a593Smuzhiyun #define SWGPE_STS (1 << 2) 90*4882a593Smuzhiyun #define HOT_PLUG_STS (1 << 1) 91*4882a593Smuzhiyun #define GPE0_EN(x) (0x90 + (x * 4)) 92*4882a593Smuzhiyun #define WADT_en (1 << 18) 93*4882a593Smuzhiyun #define GP27_EN (1 << 16) 94*4882a593Smuzhiyun #define PME_B0_EN (1 << 13) 95*4882a593Smuzhiyun #define ME_SCI_EN (1 << 12) 96*4882a593Smuzhiyun #define PME_EN (1 << 11) 97*4882a593Smuzhiyun #define BATLOW_EN (1 << 10) 98*4882a593Smuzhiyun #define PCI_EXP_EN (1 << 9) 99*4882a593Smuzhiyun #define TCOSCI_EN (1 << 6) 100*4882a593Smuzhiyun #define SWGPE_EN (1 << 2) 101*4882a593Smuzhiyun #define HOT_PLUG_EN (1 << 1) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MAINBOARD_POWER_OFF 0 104*4882a593Smuzhiyun #define MAINBOARD_POWER_ON 1 105*4882a593Smuzhiyun #define MAINBOARD_POWER_KEEP 2 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define SLEEP_STATE_S0 0 108*4882a593Smuzhiyun #define SLEEP_STATE_S3 3 109*4882a593Smuzhiyun #define SLEEP_STATE_S5 5 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct chipset_power_state { 112*4882a593Smuzhiyun uint16_t pm1_sts; 113*4882a593Smuzhiyun uint16_t pm1_en; 114*4882a593Smuzhiyun uint32_t pm1_cnt; 115*4882a593Smuzhiyun uint16_t tco1_sts; 116*4882a593Smuzhiyun uint16_t tco2_sts; 117*4882a593Smuzhiyun uint32_t gpe0_sts[4]; 118*4882a593Smuzhiyun uint32_t gpe0_en[4]; 119*4882a593Smuzhiyun uint16_t gen_pmcon1; 120*4882a593Smuzhiyun uint16_t gen_pmcon2; 121*4882a593Smuzhiyun uint16_t gen_pmcon3; 122*4882a593Smuzhiyun int prev_sleep_state; 123*4882a593Smuzhiyun uint16_t hsio_version; 124*4882a593Smuzhiyun uint16_t hsio_checksum; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif 130