1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * From coreboot soc/intel/broadwell/include/soc/lpc.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 Google Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_ARCH_LPC_H 10*4882a593Smuzhiyun #define _ASM_ARCH_LPC_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define GEN_PMCON_1 0xa0 13*4882a593Smuzhiyun #define SMI_LOCK (1 << 4) 14*4882a593Smuzhiyun #define GEN_PMCON_2 0xa2 15*4882a593Smuzhiyun #define SYSTEM_RESET_STS (1 << 4) 16*4882a593Smuzhiyun #define THERMTRIP_STS (1 << 3) 17*4882a593Smuzhiyun #define SYSPWR_FLR (1 << 1) 18*4882a593Smuzhiyun #define PWROK_FLR (1 << 0) 19*4882a593Smuzhiyun #define GEN_PMCON_3 0xa4 20*4882a593Smuzhiyun #define SUS_PWR_FLR (1 << 14) 21*4882a593Smuzhiyun #define GEN_RST_STS (1 << 9) 22*4882a593Smuzhiyun #define RTC_BATTERY_DEAD (1 << 2) 23*4882a593Smuzhiyun #define PWR_FLR (1 << 1) 24*4882a593Smuzhiyun #define SLEEP_AFTER_POWER_FAIL (1 << 0) 25*4882a593Smuzhiyun #define GEN_PMCON_LOCK 0xa6 26*4882a593Smuzhiyun #define SLP_STR_POL_LOCK (1 << 2) 27*4882a593Smuzhiyun #define ACPI_BASE_LOCK (1 << 1) 28*4882a593Smuzhiyun #define PMIR 0xac 29*4882a593Smuzhiyun #define PMIR_CF9LOCK (1 << 31) 30*4882a593Smuzhiyun #define PMIR_CF9GR (1 << 20) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif 33