1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_GPIO 10*4882a593Smuzhiyun #define __ASM_ARCH_GPIO 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define GPIO_PER_BANK 32 13*4882a593Smuzhiyun #define GPIO_BANKS 3 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct broadwell_bank_platdata { 16*4882a593Smuzhiyun uint16_t base_addr; 17*4882a593Smuzhiyun const char *bank_name; 18*4882a593Smuzhiyun int bank; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* PCH-LP GPIOBASE Registers */ 22*4882a593Smuzhiyun struct pch_lp_gpio_regs { 23*4882a593Smuzhiyun u32 own[GPIO_BANKS]; 24*4882a593Smuzhiyun u32 reserved0; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun u16 pirq_to_ioxapic; 27*4882a593Smuzhiyun u16 reserved1[3]; 28*4882a593Smuzhiyun u32 blink; 29*4882a593Smuzhiyun u32 ser_blink; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun u32 ser_blink_cmdsts; 32*4882a593Smuzhiyun u32 ser_blink_data; 33*4882a593Smuzhiyun u16 gpi_nmi_en; 34*4882a593Smuzhiyun u16 gpi_nmi_sts; 35*4882a593Smuzhiyun u32 reserved2; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun u32 gpi_route[GPIO_BANKS]; 38*4882a593Smuzhiyun u32 reserved3; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun u32 reserved4[4]; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun u32 alt_gpi_smi_sts; 43*4882a593Smuzhiyun u32 alt_gpi_smi_en; 44*4882a593Smuzhiyun u32 reserved5[2]; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun u32 rst_sel[GPIO_BANKS]; 47*4882a593Smuzhiyun u32 reserved6; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun u32 reserved9[3]; 50*4882a593Smuzhiyun u32 gpio_gc; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun u32 gpi_is[GPIO_BANKS]; 53*4882a593Smuzhiyun u32 reserved10; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun u32 gpi_ie[GPIO_BANKS]; 56*4882a593Smuzhiyun u32 reserved11; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun u32 reserved12[24]; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct { 61*4882a593Smuzhiyun u32 conf_a; 62*4882a593Smuzhiyun u32 conf_b; 63*4882a593Smuzhiyun } config[GPIO_BANKS * GPIO_PER_BANK]; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90); 66*4882a593Smuzhiyun check_member(pch_lp_gpio_regs, config[0], 0x100); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun enum { 69*4882a593Smuzhiyun CONFA_MODE_SHIFT = 0, 70*4882a593Smuzhiyun CONFA_MODE_GPIO = 1 << CONFA_MODE_SHIFT, 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun CONFA_DIR_SHIFT = 2, 73*4882a593Smuzhiyun CONFA_DIR_INPUT = 1 << CONFA_DIR_SHIFT, 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun CONFA_INVERT_SHIFT = 3, 76*4882a593Smuzhiyun CONFA_INVERT = 1 << CONFA_INVERT_SHIFT, 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun CONFA_TRIGGER_SHIFT = 4, 79*4882a593Smuzhiyun CONFA_TRIGGER_LEVEL = 1 << CONFA_TRIGGER_SHIFT, 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun CONFA_LEVEL_SHIFT = 30, 82*4882a593Smuzhiyun CONFA_LEVEL_HIGH = 1UL << CONFA_LEVEL_SHIFT, 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun CONFA_OUTPUT_SHIFT = 31, 85*4882a593Smuzhiyun CONFA_OUTPUT_HIGH = 1UL << CONFA_OUTPUT_SHIFT, 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun CONFB_SENSE_SHIFT = 2, 88*4882a593Smuzhiyun CONFB_SENSE_DISABLE = 1 << CONFB_SENSE_SHIFT, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif 92