1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __asm_arch_cpu_h 8*4882a593Smuzhiyun #define __asm_arch_cpu_h 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* CPU types */ 11*4882a593Smuzhiyun #define HASWELL_FAMILY_ULT 0x40650 12*4882a593Smuzhiyun #define BROADWELL_FAMILY_ULT 0x306d0 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Supported CPUIDs */ 15*4882a593Smuzhiyun #define CPUID_HASWELL_A0 0x306c1 16*4882a593Smuzhiyun #define CPUID_HASWELL_B0 0x306c2 17*4882a593Smuzhiyun #define CPUID_HASWELL_C0 0x306c3 18*4882a593Smuzhiyun #define CPUID_HASWELL_ULT_B0 0x40650 19*4882a593Smuzhiyun #define CPUID_HASWELL_ULT 0x40651 20*4882a593Smuzhiyun #define CPUID_HASWELL_HALO 0x40661 21*4882a593Smuzhiyun #define CPUID_BROADWELL_C0 0x306d2 22*4882a593Smuzhiyun #define CPUID_BROADWELL_D0 0x306d3 23*4882a593Smuzhiyun #define CPUID_BROADWELL_E0 0x306d4 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Broadwell bus clock is fixed at 100MHz */ 26*4882a593Smuzhiyun #define BROADWELL_BCLK 100 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define BROADWELL_FAMILY_ULT 0x306d0 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CORE_THREAD_COUNT_MSR 0x35 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define MSR_VR_CURRENT_CONFIG 0x601 33*4882a593Smuzhiyun #define MSR_VR_MISC_CONFIG 0x603 34*4882a593Smuzhiyun #define MSR_PKG_POWER_SKU 0x614 35*4882a593Smuzhiyun #define MSR_DDR_RAPL_LIMIT 0x618 36*4882a593Smuzhiyun #define MSR_VR_MISC_CONFIG2 0x636 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Latency times in units of 1024ns. */ 39*4882a593Smuzhiyun #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 40*4882a593Smuzhiyun #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 41*4882a593Smuzhiyun #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 42*4882a593Smuzhiyun #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 43*4882a593Smuzhiyun #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 44*4882a593Smuzhiyun #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun void cpu_set_power_limits(int power_limit_1_time); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif 49